user_alu.vhd

VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.

--*****************************************************************************
--*                                                                           *
--*            EuCore PCI-T32 - PCI Target Interface Core                     *
--*            (C)2000 MaxLock, Inc. All rights reserved                      *
--*                                                                           *
--*****************************************************************************
-- DESIGN  : USER_ALU
-- FILE    : USER_ALU.vhd
-- DATE    : 10.1.2001
-- REVISION: 1.1
-- DESIGNER: Tony
-- Descr   : 
-- Changes :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity USER_ALU is
   port (
      RESET : in  std_logic;
      CLK   : in  std_logic;
      ADR   : in  std_logic_vector(31 downto 0);
      ADi   : in  std_logic_vector(31 downto 0);
      ADo   : out std_logic_vector(31 downto 0);
      HIT   : in  std_logic;
      BEn   : in  std_logic_vector(3 downto 0);
      RD    : in  std_logic;
      WR    : in  std_logic;
      WE    : in  std_logic;
      NEXTD : in  std_logic;
      DRDY  : out std_logic
   );
end USER_ALU;              

architecture RTL of USER_ALU is 
   -- definition of costants
   constant Zero_32 : std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
   constant Zero_16 : std_logic_vector(15 downto 0):= "0000000000000000";
   constant HI_Z_32 : std_logic_vector(31 downto 0):= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
   constant ADD_Code: std_logic_vector(4 downto 0):= "01000";
   constant SUB_Code: std_logic_vector(4 downto 0):= "01001";
   constant AND_Code: std_logic_vector(4 downto 0):= "00001";
   constant OR_Code : std_logic_vector(4 downto 0):= "00010";
   constant XOR_Code: std_logic_vector(4 downto 0):= "00100";
   -- definition of signals
   signal A, B, Y : std_logic_vector(31 downto 0);
   signal Op : std_logic_vector(4 downto 0);
   signal Sel_A,Sel_B,Sel_Y,Sel_Op : std_logic;
   signal WE_A, WE_B, WE_Op : std_logic;
begin  
   DRDY  <= HIT;
   Sel_A <= '1' when ADR(3 downto 2)= "00"
            else '0';
   Sel_B <= '1' when ADR(3 downto 2)= "01"
            else '0';
   Sel_Y <= '1' when ADR(3 downto 2)= "10"
            else '0';
   Sel_Op <= '1' when ADR(3 downto 2)= "11"
            else '0';
   WE_A <= '1' when Sel_A='1' and WE='1' and HIT='1'
            else '0';
   WE_B <= '1' when Sel_B='1' and WE='1' and HIT='1'
            else '0';
   WE_Op <= '1' when Sel_Op='1' and WE='1' and HIT='1'
            else '0';
   -- Register A
   A_REG: process (CLK,RESET)
   begin
      if RESET = '1' then
        A <= Zero_32;   
      elsif (CLK'event and CLK='1')then
         if WE_A = '1' then
            if BEn(0)='0' then
               A(7 downto 0) <= ADi(7 downto 0);
            end if;
            if BEn(1)='0' then
               A(15 downto 8) <= ADi(15 downto 8);
            end if;
            if BEn(2)='0' then
               A(23 downto 16) <= ADi(23 downto 16);
            end if;
            if BEn(3)='0' then
               A(31 downto 24) <= ADi(31 downto 24);
            end if;
         end if;
      end if;
   end process; 
   -- Tristate data buffer
   ARegOut: ADo <= A when (Sel_A ='1' and HIT = '1' and RD = '1')
            else HI_Z_32; 

   -- Register B
   B_REG: process (CLK,RESET)
   begin
      if RESET = '1' then
        B <= Zero_32;   
      elsif (CLK'event and CLK='1')then
         if WE_B = '1' then
            if BEn(0)='0' then
               B(7 downto 0) <= ADi(7 downto 0);
            end if;
            if BEn(1)='0' then
               B(15 downto 8) <= ADi(15 downto 8);
            end if;
            if BEn(2)='0' then
               B(23 downto 16) <= ADi(23 downto 16);
            end if;
            if BEn(3)='0' then
               B(31 downto 24) <= ADi(31 downto 24);
            end if;
         end if;
      end if;
   end process;  
   -- Tristate data buffer
   BRegOut: ADo <= B when (Sel_B ='1' and HIT = '1' and RD = '1')
                  else HI_Z_32;
   -- Register Op
   Op_REG: process (CLK,RESET)
   begin
      if RESET = '1' then
        Op <= "00000";   
      elsif (CLK'event and CLK='1')then
         if WE_Op = '1' then
            if BEn(0)='0' then
               Op(4 downto 0) <= ADi(4 downto 0);
            end if;
         end if;
      end if;
   end process;  
   -- Tristate data buffer
   OpRegOut: ADo <= Zero_32(31 downto 5) & Op when (Sel_Op ='1' and HIT = '1' and RD = '1')
                    else HI_Z_32;
   -- ALU    
   ALU:process(Op,A,B)
   begin
      case Op is
         when ADD_Code =>
            Y<= A + B;  
         when SUB_Code =>
            Y<= A - B;  
         when AND_Code =>
            Y<= A and B;  
         when OR_Code =>
            Y<= A or B;  
         when XOR_Code =>
            Y<= A xor B;  
         when others =>
            Y <= A;
      end case;   
   end process;
   Y_Out: ADo <= Y when (Sel_Y ='1' and HIT = '1' and RD = '1')
                   else HI_Z_32;


end RTL;