erom_if.vhd

VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.

--*****************************************************************************
--*                                                                           *
--*            EuCore PCI-T32 - PCI Target Interface Core                     *
--*            (C)2000 MaxLock, Inc. All rights reserved                      *
--*                                                                           *
--*****************************************************************************
-- DESIGN  : PCI Expansion ROM Interface
-- FILE    : EROM_IF.vhd
-- DATE    : 10.1.2001
-- REVISION: 1.1
-- DESIGNER: Tony
-- Descr   : PCI Expansion ROM Interface with a small (16x32b)local cache 
-- Entities: EROM_IF
-- Changes : Rev. 1.0 - Doesn't support cache 
--                                                              
--            
-------------------------------------------------------------------------------
library IEEE;
library WORK;
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all; -- Arithmetic operators
use WORK.CFGSPACE_SET.all;
-- pragma translate_off
library unisim;
use unisim.all; 
-- pragma translate_on
entity EROM_IF is
   port (
      APP_RST : in std_logic;
      APP_CLK : in std_logic;
      APP_ADR : in std_logic_vector(31 downto 0);
      APP_ADI : in std_logic_vector(31 downto 0);
      APP_ADO : out std_logic_vector(31 downto 0);
      T_DRDY : out std_logic;
      T_TERM : out std_logic;
      T_EBARHIT : in std_logic;
      T_BEn : in std_logic_vector(3 downto 0);
      T_RD : in std_logic;
      T_WR : in std_logic;
      T_NEXTD : in std_logic;
      -- External ROM Interface
      ER_D  : in  std_logic_vector(7 downto 0);  -- Data Bus
      ER_A  : out std_logic_vector(18 downto 0); -- Address Bus
      ER_CEn: out std_logic;                     -- Chip Enable
      ER_OEn: out std_logic                      -- Output Enable
   );
end EROM_IF;      

architecture Behav of EROM_IF is      
   component IBUF is
     port(
         I: in std_logic;
         O: out std_logic
     ); end component;
   component OBUF is
     port(
         I: in std_logic;
         O: out std_logic
     ); end component;
   component OBUFT is
     port(
         I: in std_logic;
         O: out std_logic;
         T: in std_logic
     ); end component; 
   constant ROM_SIZE: integer := 19;  -- 19-bits = 512kB ROM Size
   constant ROM_RdCyc: integer := 4;  --  4x30ns = 120ns access time
   constant ROM_CodeOffset: std_logic_vector(ROM_SIZE-1 downto 0):= (17=>'1',others =>'0');
   type tCtrlState is (Idle,DWait,DReady,Final);   
   type tERD_State is (Idle,R0,R1,R2,R3);
   signal CtrlState: tCtrlState;
   signal ERD_State: tERD_State;
   signal ROM_DIN : std_logic_vector(7 downto 0);   
   signal ROM_D : std_logic_vector(7 downto 0);	  
   signal CacheBase : std_logic_vector(ROM_SIZE-1 downto 6);	  
   signal CacheReady : boolean; 
   signal RA,ABS_ADR : std_logic_vector (ROM_SIZE-1 downto 0);
   signal ReadData: std_logic_vector(31 downto 0); 
   signal RDWE : std_logic_vector(3 downto 0); 
   signal RDTime : integer range 0 to ROM_RdCyc;
   signal NextRD: std_logic;
   signal DRegReady : boolean; 
   signal RESET: std_logic;
begin    
   RESET <= APP_RST; 
   -- External ROM Address bus output buffers
   ADR_OutBuf: for I in 0 to ROM_SIZE-1 generate
      ASERA:OBUF port map(I => RA(I),O => ER_A(I));
   end generate;                       
   -- External ROM Input data buffers
--   DATA_InBuf: for I in 7 downto 0 generate
--      ASERD:IBUF port map(I => ER_D(I), O => ROM_DIN(I));
--   end generate;                          
   ROM_DIN<=ER_D;
   -- Internal bus data tristate buffer
   DataOut: APP_ADO <= ReadData when T_EBARHIT='1' and T_RD='1' 
                       else (others => 'Z');
   -- Name : System Controller
   -- Descr:
   Controller:process(APP_CLK,RESET)
   begin                          
      if RESET ='1' then
        CtrlState <= Idle;
      elsif APP_CLK'event and APP_CLK='1' then 
         case CtrlState is
            when Idle => 
               if T_EBARHIT ='1' then 
                  CtrlState <= DWait;
               end if;
            when DWait=> 
               if DRegReady then
                  CtrlState <= DReady;
               end if;
            when DReady =>
               if T_EBARHIT ='1' then
                  CtrlState <= Final;
               end if;
            when Final =>
               if T_EBARHIT ='0' then
                  CtrlState <= Idle;
               end if;
         end case;
      end if;
   end process; 
   -- Name : Retry Generator
   -- Descr: Generates immediate Retry when data isn't ready 
   --        or causes Disconnect with Data when data is ready
   TermGen:process (T_EBARHIT)
   begin  
      if (T_EBARHIT ='1') then
         T_TERM <= '1';
      else
         T_TERM <= '0';
      end if;
   end process;
   -- Name : Ready Generator
   -- Descr: Activates T_DRDY signal when system has prepared data
   ReadyGen:process (CtrlState, T_EBARHIT,DRegReady)
   begin  
      if DRegReady and (CtrlState = DReady) and (T_EBARHIT ='1') then
         T_DRDY <= '1';
      else
         T_DRDY <= '0';
      end if;
   end process;    
   -- Name : Data Register
   -- Descr: Keeps data read from external ROM
   DataReg:process (APP_CLK, RESET)
   begin
      if RESET='1' then	--asynchronous RESET 
         ReadData <= (others=>'0'); 
      elsif (APP_CLK'event and APP_CLK='1') then  --APP_APP_CLK rising edge
         if RDWE(0)='1' then
            ReadData(7 downto 0) <= ROM_DIN(7 downto 0);
         end if;
         if RDWE(1)='1' then
            ReadData(15 downto 8) <= ROM_DIN(7 downto 0);
         end if;
         if RDWE(2)='1' then
            ReadData(23 downto 16) <= ROM_DIN(7 downto 0);
         end if;
         if RDWE(3)='1' then
            ReadData(31 downto 24) <= ROM_DIN(7 downto 0);
         end if;
      end if;
   end process; 
   -- Name : External ROM Read Controller
   -- Descr:
   RdCtrlROM:process (APP_CLK, RESET)
   begin
      if RESET='1' then	--asynchronous RESET 
         ERD_State <= Idle;	 
      elsif (APP_CLK'event and APP_CLK='1') then  --APP_APP_CLK rising edge
         case ERD_State is
            when Idle =>
               if not(DRegReady) and T_EBARHIT='1'and CtrlState=Idle then
                  ERD_State <= R0;
               end if;
            when R0 =>
               if NextRD ='1' then
                  ERD_State <= R1;  
               end if;
            when R1 =>
               if NextRD ='1' then
                  ERD_State <= R2;  
               end if;
            when R2 =>
               if NextRD ='1' then
                  ERD_State <= R3;  
               end if;
            when R3 =>
               if NextRD ='1' then
                  ERD_State <= Idle;  
               end if;
         end case;
      end if;
   end process;
   -- Name : Read Data Register Write Enable
   -- Descr:
   pRDWE0:process (ERD_State, NextRD)
   begin
      if (ERD_State = R0)and(NextRD = '1') then
        RDWE(0) <= '1';
      else
        RDWE(0) <= '0';
      end if;
   end process; 
   -- Name : Read Data Register Write Enable
   -- Descr:
   pRDWE1:process (ERD_State, NextRD)
   begin
      if (ERD_State = R1)and(NextRD = '1') then
        RDWE(1) <= '1';
      else
        RDWE(1) <= '0';
      end if;
   end process; 
   -- Name : Read Data Register Write Enable
   -- Descr:
   pRDWE2:process (ERD_State, NextRD)
   begin
      if (ERD_State = R2)and(NextRD = '1') then
        RDWE(2) <= '1';
      else
        RDWE(2) <= '0';
      end if;
   end process; 
   -- Name : Read Data Register Write Enable
   -- Descr:
   pRDWE3:process (ERD_State, NextRD)
   begin
      if (ERD_State = R3)and(NextRD = '1') then
        RDWE(3) <= '1';
      else
        RDWE(3) <= '0';
      end if;
   end process; 
   -- Name : Read Timer
   -- Descr: Controls external ROM read access time
   ReadTimer:process (APP_CLK, RESET)
   begin
      if RESET='1' then	--asynchronous RESET 
         RDTime <= 0; 
      elsif (APP_CLK'event and APP_CLK='1') then  --APP_CLK rising edge
         if ERD_State = Idle then
            RDTime <= 0;
         elsif RDTime < (ROM_RdCyc-1) then
            RDTime <= RDTime + 1;
         else
            RDTime <= 0;
         end if;
      end if;
   end process; 
   -- Name : Next Read
   -- Descr: detects end of read time
   DetNextRD:process (RDTime)
   begin
      if RDTime = (ROM_RdCyc-1) then	
         NextRD <='1';
      else
         NextRD <='0';
      end if;
   end process;
   -- Name : External ROM Address Register
   -- Descr:  
   -- PCI Absolut address position
   ABS_ADR(EBAR_DWIDTH-1 downto 2)<= APP_ADR(EBAR_DWIDTH-1 downto 2);
   ABS_ADR(ROM_SIZE-1 downto EBAR_DWIDTH) <= (others => '0');
   ABS_ADR(1 downto 0) <= "00";
   ERA_Reg:process (APP_CLK, RESET)
   begin
      if RESET='1' then	--asynchronous RESET 
         RA <= ROM_CodeOffset;
      elsif (APP_CLK'event and APP_CLK='1') then  --APP_CLK rising edge
         if ERD_State=Idle and T_EBARHIT='1' then
            RA <= ABS_ADR+ ROM_CodeOffset;
         elsif NextRD ='1' then
            RA(1 downto 0) <= RA(1 downto 0) + 1;   
         end if;
      end if;
   end process;
   -- Name :
   -- Descr:
   pDRegReady:process (APP_CLK, RESET)
   begin
      if RESET='1' then	--asynchronous RESET 
		   DRegReady <= FALSE;
      elsif (APP_CLK'event and APP_CLK='1') then  --APP_CLK rising edge
			if DRegReady and T_EBARHIT='1' then
            DRegReady <= FALSE;
         elsif ERD_State=R3 and NextRD='1' then
            DRegReady <= TRUE;
         end if;
      end if;
   end process;
   -- Name : External ROM CEn
   -- Descr:
   pER_CEn:process (ERD_State)
   begin
      if ERD_State = Idle then
         ER_CEn <= '1';
      else
         ER_CEn <= '0';
      end if;
   end process;   
   -- Name : External ROM OEn
   -- Descr:
   pER_OEn:process (ERD_State)
   begin
      if ERD_State = Idle  then
         ER_OEn <= '1';
      else
         ER_OEn <= '0';
      end if;
   end process;
--   -- ***** CACHE *****
--   -- Name : Cache Ready Register
--   -- Descr: 
--   CacheReadyReg:process(APP_CLK,RESET)
--   begin                          
--     if RESET ='1' then
--        CacheReady <= FALSE;
--     elsif APP_CLK'event and APP_CLK='1' then 
--        CacheReady <= FALSE;
--     end if;
--   end process;
--   -- Name : Cache Base Address Register
--   -- Descr: 
--   CacheBaseReg:process(APP_CLK,RESET)
--   begin                          
--     if RESET ='1' then
--        CacheBase <= (others => '0');
--     elsif APP_CLK'event and APP_CLK='1' then 
--        
--     end if;
--   end process;
--   -- Name : Cache Hit Decoder
--   -- Descr:
--   CacheHitDet:process(CacheBase,APP_ADR(ROM_SIZE-1 downto 6))
--   begin 
--      if CacheBase = APP_ADR(ROM_SIZE-1 downto 6) then
--         CacheHit = TRUE;
--      else
--         CacheHit = FALSE;
--      end if;
--   end process;
end Behav;