cfg_decode.vhd

VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.

--*****************************************************************************
--*                                                                           *
--*            EuCore PCI-T32 - PCI Target Interface Core                     *
--*            (C)2000 MaxLock, Inc. All rights reserved                      *
--*                                                                           *
--*****************************************************************************
-- FILE    : CFG_DECODE.vhd
-- DATE    : 10.1.2001
-- REVISION: 1.1
-- DESIGNER: Tony
-- Descr   : Configuration Space Register Decoder
-- Entities: CFG_DECODE
-- Changes :
--
-- ******************************************************
-- *        Configuration Space Register Decoder        *
-- ******************************************************
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.CFGSPACE_SET.all;
entity CFG_DECODE is
   port(
      ADR         : in  std_logic_vector(7 downto 2);
      BEn         : in  std_logic_vector(3 downto 0);
      DRDY 	      : in  std_logic;
      CMD_CFGRD   : in  std_logic; -- PCI Command Config. Read
      CMD_CFGWR   : in  std_logic; -- PCI Command Config. Write
      BAR0_SIZE   : in  std_logic;
      BAR1_SIZE   : in  std_logic;
      BAR2_SIZE   : in  std_logic;
      BAR3_SIZE   : in  std_logic;
      BAR4_SIZE   : in  std_logic;
      BAR5_SIZE   : in  std_logic;
      EBAR_SIZE   : in  std_logic;
      OE_ROM      : out std_logic_vector(3 downto 0);
      ADR_ROM     : out std_logic_vector(3 downto 0);
      OE_BAR0     : out std_logic;
      OE_BAR1     : out std_logic;
      OE_BAR2     : out std_logic;
      OE_BAR3     : out std_logic;
      OE_BAR4     : out std_logic;
      OE_BAR5     : out std_logic;
      OE_EBAR     : out std_logic;
      OE_STATR    : out std_logic;
      OE_CMDR     : out std_logic;
      OE_INTR     : out std_logic;
      WE_BAR0     : out std_logic;
      WE_BAR1     : out std_logic;
      WE_BAR2     : out std_logic;
      WE_BAR3     : out std_logic;
      WE_BAR4     : out std_logic;
      WE_BAR5     : out std_logic;
      WE_EBAR     : out std_logic;
      WE_STATR    : out std_logic;
      WE_CMDR     : out std_logic;
      WE_INTR     : out std_logic
   ); 
end CFG_DECODE;

-- ******************************************************
-- *                     Architectures                  *
-- ******************************************************
architecture RTL of CFG_DECODE is
   signal OE_BAR0i : std_logic;
   signal OE_BAR1i : std_logic;
   signal OE_BAR2i : std_logic;
   signal OE_BAR3i : std_logic;
   signal OE_BAR4i : std_logic;
   signal OE_BAR5i : std_logic;
   signal OE_EBARi : std_logic;
   signal OE_STATRi : std_logic;
   signal OE_CMDRi : std_logic;
   signal OE_INTRi : std_logic;
   signal OE_BRegs : std_logic; 
begin
   -- Address Remap for 0x40-0xFF to reserved position
   pRAGEN: process(ADR)
   begin
      if (ADR(7)='1' or ADR(6)='1') then
         ADR_ROM <= ROMADR_REMAP;
      else
         ADR_ROM <= ADR(5 downto 2);
      end if;
   end process pRAGEN;
   -- BAR0
   OE_BAR0i <= '1' when BAR0_PRESENT and (ADR(5 downto 2)="0100") and (CMD_CFGRD='1') and 
                        (not (BAR0_SIZE='1')and (DRDY='1'))
                   else '0';
   OE_BAR0 <= OE_BAR0i;
   -- BAR1
   OE_BAR1i <= '1' when BAR1_PRESENT and (ADR(5 downto 2)="0101") and (CMD_CFGRD='1') and 
                        (not (BAR1_SIZE='1')and (DRDY='1'))
                else '0';
   OE_BAR1 <= OE_BAR1i;
   -- BAR2
   OE_BAR2i <= '1' when BAR2_PRESENT and (ADR(5 downto 2)="0110") and (CMD_CFGRD='1') and 
                        (not (BAR2_SIZE='1')and (DRDY='1'))
                else '0';
   OE_BAR2 <= OE_BAR2i;
   -- BAR3
   OE_BAR3i <= '1' when BAR3_PRESENT and (ADR(5 downto 2)="0111") and (CMD_CFGRD='1') and 
                        (not (BAR3_SIZE='1')and (DRDY='1'))
                else '0';
   OE_BAR3 <= OE_BAR3i;
   -- BAR4
   OE_BAR4i <= '1' when BAR4_PRESENT and (ADR(5 downto 2)="1000") and (CMD_CFGRD='1') and 
                        (not (BAR4_SIZE='1')and (DRDY='1'))
                else '0';
   OE_BAR4 <= OE_BAR4i;
   -- BAR5
   OE_BAR5i <= '1' when BAR5_PRESENT and (ADR(5 downto 2)="1001") and (CMD_CFGRD='1') and
                        (not (BAR5_SIZE='1')and (DRDY='1'))
                else '0';
   OE_BAR5 <= OE_BAR5i;
   -- Expansion Rom BAR
   OE_EBARi <= '1' when EBAR_PRESENT and (ADR(5 downto 2)="1100") and (CMD_CFGRD='1') and 
                        (not (EBAR_SIZE='1')and (DRDY='1'))
                else '0';
   OE_EBAR <= OE_EBARi;
   -- Status
   OE_STATRi<= '1' when (ADR(5 downto 2)="0001") and (CMD_CFGRD='1')and (DRDY='1') 
                   else '0';
   OE_STATR <= OE_STATRi;                   
   -- Command
   OE_CMDRi <= '1' when (ADR(5 downto 2)="0001") and (CMD_CFGRD='1')and (DRDY='1') 
                   else '0';
   OE_CMDR <= OE_CMDRi;                  
   -- Interrupt Line
   OE_INTRi <= '1' when (ADR(5 downto 2)="1111") and (CMD_CFGRD='1')and (DRDY='1') 
                   else '0';
   OE_INTR <= OE_INTRi; 
   -- ROM Based Parameters                  
   OE_BRegs <= OE_BAR0i or OE_BAR1i or OE_BAR2i or OE_BAR3i or OE_BAR4i or OE_BAR5i or OE_EBARi;
   OE_ROM(0) <= CMD_CFGRD and DRDY and not(OE_BRegs or OE_CMDRi or OE_INTRi);
   OE_ROM(1) <= CMD_CFGRD and DRDY and not(OE_BRegs or OE_CMDRi);
   OE_ROM(2) <= CMD_CFGRD and DRDY and not(OE_BRegs or OE_STATRi);
   OE_ROM(3) <= CMD_CFGRD and DRDY and not(OE_BRegs or OE_STATRi);
   --
   WE_BAR0 <= '1' when BAR0_PRESENT and (ADR(5 downto 2)="0100") and (CMD_CFGWR='1')and (DRDY='1')
                  else '0';
   --
   WE_BAR1 <= '1' when BAR1_PRESENT and (ADR(5 downto 2)="0101") and (CMD_CFGWR='1')and (DRDY='1')
                  else '0';
   --
   WE_BAR2 <= '1' when BAR2_PRESENT and (ADR(5 downto 2)="0110") and (CMD_CFGWR='1')and (DRDY='1')
                  else '0';
   --
   WE_BAR3 <= '1' when BAR3_PRESENT and (ADR(5 downto 2)="0111") and (CMD_CFGWR='1')and (DRDY='1')
                  else '0';
   --
   WE_BAR4 <= '1' when BAR4_PRESENT and (ADR(5 downto 2)="1000") and (CMD_CFGWR='1')and (DRDY='1')
                  else '0';
   --
   WE_BAR5 <= '1' when BAR5_PRESENT and (ADR(5 downto 2)="1001") and (CMD_CFGWR='1')and (DRDY='1')
                  else '0';
   --
   WE_EBAR <= '1' when (ADR(5 downto 2)="1100") and (CMD_CFGWR='1')and (DRDY='1')
                  else '0';
   --
   WE_STATR <= '1' when (ADR(5 downto 2)="0001") and (CMD_CFGWR='1')and (DRDY='1')
                   else '0';
   --
   WE_CMDR <= '1' when (ADR(5 downto 2)="0001") and (CMD_CFGWR='1')and (DRDY='1') 
                   else '0';
   --
   WE_INTR <= '1' when (ADR(5 downto 2)="1111") and (CMD_CFGWR='1') and (BEn(0)='0')and (DRDY='1')
                   else '0';
end RTL;