pci_io_virtex.vhd

VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.

   signal LPERRni  : std_logic;
   signal LSERRni  : std_logic;
--   signal FRAMEno:  std_logic;
--   signal IRDYno :  std_logic;  
   signal DEVSELno : std_logic; 
   signal TRDYno :  std_logic;  
   signal STOPno : std_logic; 
   signal L_OT_AD  : std_logic;
   signal OT_PAR,ParOut,PARod : std_logic; 
   signal Log1,Log0 : std_logic; 
   signal OT_ADo: std_logic_vector(31 downto 0);
   signal NEW_OT_ADo: std_logic;
   signal OT_CBE: std_logic_vector(3 downto 0);
   signal CE_ADob:std_logic_vector(3 downto 0);
   signal CBEc: std_logic_vector(3 downto 0);
   signal CBEod: std_logic_vector(3 downto 0);   
   signal ADil: std_logic_vector(31 downto 0);
   signal ADol: std_logic_vector(31 downto 0); 
   signal ADOT: std_logic_vector(31 downto 0);
   signal OT_IRDY: std_logic; 
   signal PERRno: std_logic;
   signal SERRno: std_logic;
   signal OT_PERR : std_logic; 
   signal OT_INTA : std_logic;  
   signal T_OTAD, M_OTAD : std_logic;  
   -- Component Attributes
   attribute IOB : string;
   attribute INIT : string;

begin
   Log0 <= '0';
   Log1 <= '1';
   -- #### RESET ####     
   IB1: IBUF port map(I => RSTn_p, O => RESETn);
   AS1:RESETi <= not(RESETn);
   AS2:RESET  <= RESETi;
   -- #### Clock Buffer ####
   CB1: BUFGP port map(I => CLK_p, O => CLKi);-- Primary clock buffer 
   AS3:CLK <= CLKi;
   -- #### TARGET SIGNALS ####
   -- IDSEL IOB
   IB2: IBUF port map(I => IDSEL_p, O => IDSELil);
   ASIO2:IDSELi <= IDSELil;                                                            -- Direct Input
   IFF2: FDCE port map(C=>CLKi, D=>IDSELil, Q=>IDSELid, CE=>Log1, CLR=>RESETi);	         -- Clocked Input
   -- FRAME# IOB
   IB3: IBUF port map(I => FRAMEn_p, O => FRAMEnil);                                   -- Direct Input
   IFF3: FDPE  port map(C=> CLKi, D => FRAMEnil, Q => FRAMEnid,CE=>Log1,PRE=>RESETi);	   -- Clocked Input
   ASIO3:FRAMEni <= FRAMEnil;
   -- IRDY# IOB
   IB4: IBUF port map(I => IRDYn_p, O => IRDYnil); -- Direct Input
   IFF4: FDPE  port map(C=> CLKi, D => IRDYnil, Q => IRDYnid,CE=>Log1,PRE =>RESETi);	   -- Clocked Input
   ASIO4:IRDYni <= IRDYnil;
   -- TRDY# IOB
   IB5: IBUF port map(I => TRDYn_p, O => TRDYnil); -- Direct Input
   ASIO5:TRDYni <= TRDYnil;
   IFF5: FDPE  port map(C=> CLKi, D => TRDYnil, Q => TRDYnid,CE=>Log1,PRE=>RESETi);	   -- Clocked Input
   OFF5: FDPE  port map(C=> CLKi, D => NEW_TRDYno, Q => TRDYno,CE=>Log1,PRE =>RESETi);	   -- Clocked Input
   OB5: OBUFT port map(I=> TRDYno, O => TRDYn_p, T => OT_TRDY);
   -- STOP# IOB
   IB6: IBUF port map(I => STOPn_p, O => STOPnil);  -- Direct Input
   IFF6: FDPE  port map(C=> CLKi, D => STOPnil, Q => STOPnid, CE=>Log1, PRE=>RESETi);    -- Clocked Input
   OFF6: FDPE  port map(C=> CLKi, D => NEW_STOPno, Q => STOPno,CE=>Log1,PRE =>RESETi);	   -- Clocked Input
   OB6: OBUFT port map(I=> STOPno, O => STOPn_p, T => OT_STOP);
   ASIO6: STOPni <= STOPnil;
   -- DEVSEL# IOB
   IB7: IBUF port map(I => DEVSELn_p, O => DEVSELnil);    				-- Direct Input
   IFF7: FDPE  port map(C=> CLKi, D => DEVSELnil, Q => DEVSELnid, CE=>Log1, PRE=>RESETi);    -- Clocked Input
   OFF7: FDPE  port map(C=> CLKi, D => NEW_DEVSELno, Q => DEVSELno,CE=>Log1,PRE =>RESETi);	   -- Clocked Input
   OB7: OBUFT port map(I=> DEVSELno, O => DEVSELn_p, T => OT_DEVSEL);
   ASIO7: DEVSELni <= DEVSELnil;
   
   -- Interrupt Pin INTA# = Open Drain Output 
   TFF8: FDPE  port map(C=> CLKi, D => INTAno, Q => OT_INTA,CE=>Log1,PRE =>RESETi);	   -- Clocked Input
   
   OB8: OBUFT port map(I=> Log0, O => INTAn_p  , T =>OT_INTA);
   --  C/BE#[3:0] Input 
   CBEBUF:for I in 0 to 3 generate
      IBCBE: IBUF port map(I => CBE_p(I), O => CBEc(I));                                  -- Input Buffer
      ASCBE: CBEi(I)<= CBEc(I);
      IFFCBE: FDCE  port map(C=> CLKi, D => CBEc(I), Q => CBEid(I), CE=>Log1, CLR=>RESETi); -- Clocked Input
   end generate;

   LPCI0 : PCILOGIC port map ( 
      PCI_CE => CE_ADob(0),
      IRDY   => IRDYnil,
      T_CE_RDY   => T_CE_ADoRDY,
      DIR_CEo    => CE_ADo
      );
   LPCI1 : PCILOGIC port map ( 
      PCI_CE => CE_ADob(1),
      IRDY   => IRDYnil,
      T_CE_RDY   => T_CE_ADoRDY,
      DIR_CEo    => CE_ADo
      );
   LPCI2 : PCILOGIC port map ( 
      PCI_CE => CE_ADob(2),
      IRDY   => IRDYnil,
      T_CE_RDY   => T_CE_ADoRDY,
      DIR_CEo    => CE_ADo
      );
   LPCI3 : PCILOGIC port map ( 
      PCI_CE => CE_ADob(3),
      IRDY   => IRDYnil,
      T_CE_RDY   => T_CE_ADoRDY,
      DIR_CEo    => CE_ADo
      );
   -- DATA Output buffer control 
   ASADT0: NEW_OT_ADo <= T_OT_AD;
   -- PCI Data Bus
   ADBUF0: for S in 0 to 7 generate
      IBAD : IBUF port map(I=>AD_p(S), O=>ADil(S));                                       -- Input Buffer
      IFF : FDCE port map(C=>CLKi, D=>ADil(S), Q=>ADi(S), CE=>Log1, CLR=>RESETi);         -- Clocked Input
      OFF : FDCE port map(C=>CLKi, D=>ADo(S), Q=>ADol(S), CE=>CE_ADob(0), CLR=>RESETi);       -- Clocked Output
      TFF : FDPE  port map(C=> CLKi, D => NEW_OT_ADo, Q => OT_ADo(S),CE=>Log1,PRE =>RESETi);	   -- Clocked Input
      OBAD : OBUFT port map(I=>ADol(S), O=> AD_p(S),  T=>OT_ADo(S));                         -- Output Buffer
   end generate;   
   ADBUF1: for S in 8 to 15 generate
      IBAD : IBUF port map(I=>AD_p(S), O=>ADil(S));                                       -- Input Buffer
      IFFAD : FDCE port map(C=>CLKi, D=>ADil(S), Q=>ADi(S), CE=>Log1, CLR=>RESETi);         -- Clocked Input
      OFFAD : FDCE port map(C=>CLKi, D=>ADo(S), Q=>ADol(S), CE=>CE_ADob(1), CLR=>RESETi);       -- Clocked Output
      TFF : FDPE  port map(C=> CLKi, D => NEW_OT_ADo, Q => OT_ADo(S),CE=>Log1,PRE =>RESETi);	   -- Clocked Input
      OBAD : OBUFT port map(I=>ADol(S), O=> AD_p(S),  T=>OT_ADo(S));                         -- Output Buffer
   end generate;   
   ADBUF2: for S in 16 to 23 generate
      IBAD : IBUF port map(I=>AD_p(S), O=>ADil(S));                                       -- Input Buffer
      IFFAD : FDCE port map(C=>CLKi, D=>ADil(S), Q=>ADi(S), CE=>Log1, CLR=>RESETi);         -- Clocked Input
      OFFAD : FDCE port map(C=>CLKi, D=>ADo(S), Q=>ADol(S), CE=>CE_ADob(2), CLR=>RESETi);       -- Clocked Output
      TFF : FDPE  port map(C=> CLKi, D => NEW_OT_ADo, Q => OT_ADo(S),CE=>Log1,PRE =>RESETi);	   -- Clocked Input
      OBAD : OBUFT port map(I=>ADol(S), O=> AD_p(S),  T=>OT_ADo(S));                         -- Output Buffer
   end generate;   
   ADBUF3: for S in 24 to 31 generate
      IBAD  : IBUF port map(I=>AD_p(S), O=>ADil(S));                                       -- Input Buffer
      IFFAD : FDCE port map(C=>CLKi, D=>ADil(S), Q=>ADi(S), CE=>Log1, CLR=>RESETi);         -- Clocked Input
      OFFAD : FDCE port map(C=>CLKi, D=>ADo(S), Q=>ADol(S), CE=>CE_ADob(3), CLR=>RESETi);       -- Clocked Output
      TFF   : FDPE  port map(C=> CLKi, D => NEW_OT_ADo, Q => OT_ADo(S),CE=>Log1,PRE =>RESETi);	   -- Clocked Input
      OBAD  : OBUFT port map(I=>ADol(S), O=> AD_p(S),  T=>OT_ADo(S));                         -- Output Buffer
   end generate;   

   -- PARITY
	PG: GEN_PAR	port map(
   		RESET    => RESETi,
   		CLK      => CLKi,
   		CE_ADo   => CE_ADob(2),
   		ADo      => ADo,
   		CBEi     => CBEc,
   		NEW_PARo => ParOut
         );
   
   IBPAR : IBUF port map(I=> PAR_p, O=> LPARi);
   ASPAR : PARi <= LPARi;
   IFFPAR: FDCE port map(C => CLKi, D => LPARi, Q => PARid, CE => Log1, CLR => RESETi);
   OTADFF: FDPE  port map(C=> CLKi, D => NEW_OT_ADo, Q => L_OT_AD,CE=>Log1,PRE =>RESETi);
   TFFPAR: FDPE port map(C => CLKi, D => L_OT_AD, Q => OT_PAR, CE => Log1, PRE =>RESETi);
   OFFPAR: FDCE port map(Q => PARod, D => ParOut, C => CLKi, CE => Log1, CLR => RESETi);
   OBPAR : OBUFT port map(I=> PARod, O=> PAR_p,  T=>OT_PAR);   
   -- Parity Error Reporting
   OFFPERR : FDCE port map(C => CLKi, D => NEW_PERRno, Q => PERRno, CE => Log1, CLR => RESETi);
   TFFERR: FDPE port map(C => CLKi, D => NEW_OTPERR, Q => OT_PERR, CE => Log1, PRE =>RESETi);
   PO2: OBUFT port map(I => PERRno, O => PERRn_p, T => OT_PERR);  	  	 	  	
--   PO2: OBUFT port map(I => Log0, O => PERRn_p, T => Log1);  	  	 	  	
   PI2: IBUF port map(I => PERRn_p, O => LPERRni);    				-- Direct Input
   PERRni <= LPERRni;
   IFFPERR : FDCE port map(C => CLKi, D =>LPERRni, Q =>PERRnid, CE => Log1, CLR => RESETi);
   
   -- System Error Reporting
   FFTSERR: FDPE port map(C => CLKi, D => NEW_SERRno, Q => SERRno, CE => Log1, PRE =>RESETi);
   PO3: OBUFT port map(I => Log0, O => SERRn_p, T => SERRno);  	  			
   PI3: IBUF port map(I => SERRn_p, O => LSERRni);    				-- Direct Input
   SERRni <= LSERRni;
   IFFSERR : FDCE port map(C => CLKi, D =>LSERRni, Q =>SERRnid, CE => Log1, CLR => RESETi);
   -- Bus Hanshake Signals
end Struct;                          
--
architecture RTL of PCILOGIC is
begin
   PCI_CE <= DIR_CEo or (T_CE_RDY and not IRDY);
end RTL;