ram2rw256xw.vhd

8-1024可变点数FFT/IFFT变换,VHDL语言设计, 仿真通过,可以很容易综合.

--************************************************************
--************************************************************
--*----------------------------------------------------------*
--*|Version                          :2.0                    |
--*|Date of Last Revision            :02/23/2001             |
--*----------------------------------------------------------*
--************************************************************
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved.
--************************************************************
-- Warning: This file is protected by Federal Copyright Law,
-- with all rights reserved. It is unlawful to reproduce
-- any parts of this file, in any form, without expressed
-- written permission from Drey Enterprises Inc. This Copyright
-- is actively enforced.
--************************************************************
--************************************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity RAM2RW256xW is
    generic(
        WORD_WIDTH     :integer := 24
    );
    port(
        clk            :in std_logic;
        pass           :in std_logic_vector(3 downto 0);
        wea            :in std_logic;
        web            :in std_logic;
        addra          :in std_logic_vector(7 downto 0);
        addrb          :in std_logic_vector(7 downto 0);
        dataina        :in std_logic_vector(WORD_WIDTH-1 downto 0);
        datainb        :in std_logic_vector(WORD_WIDTH-1 downto 0);
        dataouta       :out std_logic_vector(WORD_WIDTH-1 downto 0);
        dataoutb       :out std_logic_vector(WORD_WIDTH-1 downto 0)
     );
end RAM2RW256xW;

architecture behavior of RAM2RW256xW is

   COMPONENT lpm_ram_dp
   GENERIC (
      LPM_WIDTH            : INTEGER := WORD_WIDTH;
      LPM_WIDTHAD          : INTEGER := 8;
      LPM_NUMWORDS         : INTEGER := 256;
      LPM_INDATA           : STRING := "REGISTERED";
      LPM_OUTDATA          : STRING := "REGISTERED";
      LPM_RDADDRESS_CONTROL: STRING := "REGISTERED";
      LPM_WRADDRESS_CONTROL: STRING := "REGISTERED";
      LPM_FILE             : STRING := "UNUSED";
      LPM_TYPE             : STRING := "LPM_RAM_DP";
      LPM_HINT             : STRING := "UNUSED");    
   PORT (
        RDCLOCK     : in std_logic := '0';
        RDCLKEN     : in std_logic := '1';
        RDADDRESS   : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
        RDEN        : in std_logic := '1';
        DATA        : in std_logic_vector(LPM_WIDTH-1 downto 0);
        WRADDRESS   : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
        WREN        : in std_logic;
        WRCLOCK     : in std_logic := '0';
        WRCLKEN     : in std_logic := '1';
        Q           : out std_logic_vector(LPM_WIDTH-1 downto 0)
   );
   END COMPONENT;

   signal dataout_u1 :std_logic_vector(WORD_WIDTH-1 downto 0);
   signal dataout_u2 :std_logic_vector(WORD_WIDTH-1 downto 0);
   signal dataout_u3 :std_logic_vector(WORD_WIDTH-1 downto 0);
   signal dataout_u4 :std_logic_vector(WORD_WIDTH-1 downto 0);
   signal zero,one   :std_logic;
   signal addra_dly  :std_logic_vector(7 downto 0);
        
begin

     one <= '1';
     zero <= '0';

     -- hold address for a cycle to align with ram delay
     process
     begin
         wait until clk'event and clk = '1';
         addra_dly <= addra;
     end process;

     process(pass,addra_dly,
             dataout_u1,dataout_u2,dataout_u3,dataout_u4)
     begin
         case pass is
            when "0000" => 
                dataouta <= dataout_u1;
                dataoutb <= dataout_u2;
            when "0001" => 
                if (addra_dly(7) = '1') then
                    dataouta <= dataout_u3;
                    dataoutb <= dataout_u4;
                else
                    dataouta <= dataout_u1;
                    dataoutb <= dataout_u2;
                end if;
            when "0010" => 
                if (addra_dly(6) = '1') then
                    dataouta <= dataout_u3;
                    dataoutb <= dataout_u4;
                else
                    dataouta <= dataout_u1;
                    dataoutb <= dataout_u2;
                end if;
            when "0011" => 
                if (addra_dly(5) = '1') then
                    dataouta <= dataout_u3;
                    dataoutb <= dataout_u4;
                else
                    dataouta <= dataout_u1;
                    dataoutb <= dataout_u2;
                end if;
            when "0100" => 
                if (addra_dly(4) = '1') then
                    dataouta <= dataout_u3;
                    dataoutb <= dataout_u4;
                else
                    dataouta <= dataout_u1;
                    dataoutb <= dataout_u2;
                end if;
            when "0101" => 
                if (addra_dly(3) = '1') then
                    dataouta <= dataout_u3;
                    dataoutb <= dataout_u4;
                else
                    dataouta <= dataout_u1;
                    dataoutb <= dataout_u2;
                end if;
             when "0110" => 
                if (addra_dly(2) = '1') then
                    dataouta <= dataout_u3;
                    dataoutb <= dataout_u4;
                else
                    dataouta <= dataout_u1;
                    dataoutb <= dataout_u2;
                end if;
             when "0111" => 
                if (addra_dly(1) = '1') then
                    dataouta <= dataout_u3;
                    dataoutb <= dataout_u4;
                else
                    dataouta <= dataout_u1;
                    dataoutb <= dataout_u2;
                end if;
             when others => 
                dataouta <= dataout_u1;
                dataoutb <= dataout_u4; 
         end case;
     end process;

    a1:lpm_ram_dp
    GENERIC map(
      LPM_WIDTH              => WORD_WIDTH,
      LPM_WIDTHAD            => 8,
      LPM_NUMWORDS           => 256,
      LPM_INDATA             => "REGISTERED",
      LPM_OUTDATA            => "UNREGISTERED",
      LPM_RDADDRESS_CONTROL  => "REGISTERED",
      LPM_WRADDRESS_CONTROL  => "REGISTERED",
      LPM_FILE               => "UNUSED",
      LPM_TYPE               => "LPM_RAM_DP",
      LPM_HINT               => "UNUSED")    
    port map(
        RDCLOCK      => clk,
        RDCLKEN      => one,
        RDADDRESS    => addra,
        RDEN         => one,
        DATA         => dataina(WORD_WIDTH-1 downto 0),
        WRADDRESS    => addra,
        WREN         => wea,
        WRCLOCK      => clk,
        WRCLKEN      => one,
        Q            => dataout_u1(WORD_WIDTH-1 downto 0)
     );

    a2:lpm_ram_dp
    GENERIC map(
      LPM_WIDTH              => WORD_WIDTH,
      LPM_WIDTHAD            => 8,
      LPM_NUMWORDS           => 256,
      LPM_INDATA             => "REGISTERED",
      LPM_OUTDATA            => "UNREGISTERED",
      LPM_RDADDRESS_CONTROL  => "REGISTERED",
      LPM_WRADDRESS_CONTROL  => "REGISTERED",
      LPM_FILE               => "UNUSED",
      LPM_TYPE               => "LPM_RAM_DP",
      LPM_HINT               => "UNUSED")    
    port map(
        RDCLOCK      => clk,
        RDCLKEN      => one,
        RDADDRESS    => addrb,
        RDEN         => one,
        DATA         => dataina(WORD_WIDTH-1 downto 0),
        WRADDRESS    => addra,
        WREN         => wea,
        WRCLOCK      => clk,
        WRCLKEN      => one,
        Q            => dataout_u2(WORD_WIDTH-1 downto 0)
     );

    a3:lpm_ram_dp
    GENERIC map(
      LPM_WIDTH              => WORD_WIDTH,
      LPM_WIDTHAD            => 8,
      LPM_NUMWORDS           => 256,
      LPM_INDATA             => "REGISTERED",
      LPM_OUTDATA            => "UNREGISTERED",
      LPM_RDADDRESS_CONTROL  => "REGISTERED",
      LPM_WRADDRESS_CONTROL  => "REGISTERED",
      LPM_FILE               => "UNUSED",
      LPM_TYPE               => "LPM_RAM_DP",
      LPM_HINT               => "UNUSED")    
    port map(
        RDCLOCK      => clk,
        RDCLKEN      => one,
        RDADDRESS    => addra,
        RDEN         => one,
        DATA         => datainb(WORD_WIDTH-1 downto 0),
        WRADDRESS    => addrb,
        WREN         => web,
        WRCLOCK      => clk,
        WRCLKEN      => one,
        Q            => dataout_u3(WORD_WIDTH-1 downto 0)
     );

    a4:lpm_ram_dp
    GENERIC map(
      LPM_WIDTH              => WORD_WIDTH,
      LPM_WIDTHAD            => 8,
      LPM_NUMWORDS           => 256,
      LPM_INDATA             => "REGISTERED",
      LPM_OUTDATA            => "UNREGISTERED",
      LPM_RDADDRESS_CONTROL  => "REGISTERED",
      LPM_WRADDRESS_CONTROL  => "REGISTERED",
      LPM_FILE               => "UNUSED",
      LPM_TYPE               => "LPM_RAM_DP",
      LPM_HINT               => "UNUSED")    
    port map(
        RDCLOCK      => clk,
        RDCLKEN      => one,
        RDADDRESS    => addrb,
        RDEN         => one,
        DATA         => datainb(WORD_WIDTH-1 downto 0),
        WRADDRESS    => addrb,
        WREN         => web,
        WRCLOCK      => clk,
        WRCLKEN      => one,
        Q            => dataout_u4(WORD_WIDTH-1 downto 0)
     );

end behavior;