ram2rw256xm.vhd

8-1024可变点数FFT/IFFT变换,VHDL语言设计, 仿真通过,可以很容易综合.

--************************************************************
--************************************************************
--*----------------------------------------------------------*
--*|Version                          :1.0                    |
--*|Date of Last Revision            :12/23/1998             |
--*----------------------------------------------------------*
--************************************************************
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved.
--************************************************************
-- Warning: This file is protected by Federal Copyright Law,
-- with all rights reserved. It is unlawful to reproduce
-- any parts of this file, in any form, without expressed
-- written permission from Drey Enterprises Inc. This Copyright
-- is actively enforced.
--************************************************************
--************************************************************

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity RAM2RW256xM is
    generic(
        WORD_WIDTH     :integer := 32
    );
    port(
        clk            :in std_logic;
        pass           :in std_logic_vector(3 downto 0); -- unused except in altera
        wea            :in std_logic;
        web            :in std_logic;
        addra          :in std_logic_vector(7 downto 0);
        addrb          :in std_logic_vector(7 downto 0);
        dataina        :in std_logic_vector(WORD_WIDTH-1 downto 0);
        datainb        :in std_logic_vector(WORD_WIDTH-1 downto 0);
        dataouta       :out std_logic_vector(WORD_WIDTH-1 downto 0);
        dataoutb       :out std_logic_vector(WORD_WIDTH-1 downto 0)
     );
end RAM2RW256xM;

architecture behavior of RAM2RW256xM is
-- This architecture is to be replaced with technology
-- dependant RAM, and is black-boxed during synthesis
-- For instance, An LSI replacement is M10P222HS (256x32)

    type ram_type is array(0 to 255) of
         Std_Logic_Vector(WORD_WIDTH-1 downto 0);
    signal ram:ram_type;
        
begin
   
    process
    begin
       wait until clk'event and clk='1';
       dataouta <= ram(CONV_INTEGER(addra));
       dataoutb <= ram(CONV_INTEGER(addrb));
    end process;

    process
    begin
       wait until clk'event and clk='1';
       if (wea = '1') then
          ram(CONV_INTEGER(addra)) <= dataina;
       end if;
       if (web = '1') then
          ram(CONV_INTEGER(addrb)) <= datainb;
       end if;
    end process;

end behavior;