sincos_rom.vhd

8-1024可变点数FFT/IFFT变换,VHDL语言设计, 仿真通过,可以很容易综合.

--************************************************************
--************************************************************
--*----------------------------------------------------------*
--*|Version                               :1.0               |
--*|Date of Last Revision                 :12/23/1998        |
--*----------------------------------------------------------*
--************************************************************
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved.
--************************************************************
-- Warning: This file is protected by Federal Copyright Law,
-- with all rights reserved. It is unlawful to reproduce
-- any parts of this file, in any form, without expressed
-- written permission from Drey Enterprises Inc. This Copyright
-- is actively enforced.
--************************************************************
--************************************************************

library IEEE;
use IEEE.std_logic_1164.all;

-- store full wave

entity SINCOS_ROM is
    generic(WORD_WIDTH     :integer := 32);
    port(
        clk                :in std_logic;
        addr               :in std_logic_vector(7 downto 0);
        rad4               :in std_logic;
        W1_sin_data        :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
        W1_cos_data        :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
        W2_sin_data        :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
        W2_cos_data        :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
        W3_sin_data        :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
        W3_cos_data        :out std_logic_vector(WORD_WIDTH/2-1 downto 0)
    );
end SINCOS_ROM;

architecture behavior of SINCOS_ROM is

    component SINROM128_W1 
    port(
        addr         :in std_logic_vector(6 downto 0);
        sin_w1       :out std_logic_vector(31 downto 0)
    );
    end component;

    component COSROM128_W1 
    port(
        addr         :in std_logic_vector(6 downto 0);
        cos_w1       :out std_logic_vector(31 downto 0)
    );
    end component;

    component SINROM256_W1 
    port(
        addr               :in std_logic_vector(7 downto 0);
        sin_w1             :out std_logic_vector(31 downto 0)
    );
    end component;

    component COSROM256_W1 
    port(
        addr                :in std_logic_vector(7 downto 0);
        cos_w1              :out std_logic_vector(31 downto 0)
    );
    end component;

    component SINROM256_W2 
    port(
        addr                :in std_logic_vector(7 downto 0);
        sin_w2              :out std_logic_vector(31 downto 0)
    );
    end component;

    component COSROM256_W2 
    port(
        addr                :in std_logic_vector(7 downto 0);
        cos_w2              :out std_logic_vector(31 downto 0)
    );
    end component;

    component SINROM256_W3 
    port(
        addr                :in std_logic_vector(7 downto 0);
        sin_w3              :out std_logic_vector(31 downto 0)
    );
    end component;

    component COSROM256_W3 
    port(
        addr                :in std_logic_vector(7 downto 0);
        cos_w3              :out std_logic_vector(31 downto 0)
    );
    end component;
    
    signal W1_sin_data_sig     :std_logic_vector(31 downto 0);
    signal W1_cos_data_sig     :std_logic_vector(31 downto 0);
    signal W1_sin128_data_sig  :std_logic_vector(31 downto 0);
    signal W1_cos128_data_sig  :std_logic_vector(31 downto 0);
    signal W1_sin256_data_sig  :std_logic_vector(31 downto 0);
    signal W1_cos256_data_sig  :std_logic_vector(31 downto 0);
    signal W2_sin_data_sig     :std_logic_vector(31 downto 0);
    signal W2_cos_data_sig     :std_logic_vector(31 downto 0);
    signal W3_sin_data_sig     :std_logic_vector(31 downto 0);
    signal W3_cos_data_sig     :std_logic_vector(31 downto 0);

    signal pwrdn_addr          :std_logic_vector(7 downto 0);

begin

    --Power down the other ROM's during rad2 operation
    --power is not a concern, but this will help a little
    process(rad4,addr)
    begin 
        if (rad4 = '1') then
            pwrdn_addr <= addr;
        else
            pwrdn_addr <= "00000000";
        end if;
    end process;

    process
    begin
        wait until clk'event and clk = '1';
        W1_sin_data <= W1_sin_data_sig(31 downto 32-WORD_WIDTH/2);
        W1_cos_data <= W1_cos_data_sig(31 downto 32-WORD_WIDTH/2);
        W2_sin_data <= W2_sin_data_sig(31 downto 32-WORD_WIDTH/2);
        W2_cos_data <= W2_cos_data_sig(31 downto 32-WORD_WIDTH/2);
        W3_sin_data <= W3_sin_data_sig(31 downto 32-WORD_WIDTH/2);
        W3_cos_data <= W3_cos_data_sig(31 downto 32-WORD_WIDTH/2);
    end process;

    process(rad4,W1_sin128_data_sig,W1_cos128_data_sig,
                 W1_sin256_data_sig,W1_cos256_data_sig)
    begin
        if (rad4 = '1') then
            W1_sin_data_sig <= W1_sin256_data_sig;
            W1_cos_data_sig <= W1_cos256_data_sig;
        else
            W1_sin_data_sig <= W1_sin128_data_sig;
            W1_cos_data_sig <= W1_cos128_data_sig;
        end if;
    end process;

    sin128_w1:SINROM128_W1
    port map(
        addr => addr(6 downto 0),
        sin_w1 => W1_sin128_data_sig
    );

    cos128_w1:COSROM128_W1
    port map(
        addr => addr(6 downto 0),
        cos_w1 => W1_cos128_data_sig
    );

    sin256_w1:SINROM256_W1
    port map(
        addr => pwrdn_addr,
        sin_w1 => W1_sin256_data_sig
    );

    cos256_w1:COSROM256_W1
    port map(
        addr => pwrdn_addr,
        cos_w1 => W1_cos256_data_sig
    );

    sin_w2:SINROM256_W2
    port map(
        addr => pwrdn_addr,
        sin_w2 => W2_sin_data_sig
    );

    cos_w2:COSROM256_W2
    port map(
        addr => pwrdn_addr,
        cos_w2 => W2_cos_data_sig
    );

    sin_w3:SINROM256_W3
    port map(
        addr => pwrdn_addr,
        sin_w3 => W3_sin_data_sig
    );

    cos_w3:COSROM256_W3
    port map(
        addr => pwrdn_addr,
        cos_w3 => W3_cos_data_sig
    );

end behavior;