mulv.vhd

这是用VHDL语言(硬件描述语言)写的一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT).全同步设计,低门数.可以用于多媒体及打印应用领域.

---------------------------------------------------------------------------
-- Project: DCT 
-- Revision: 1.0 
-- Date of last Revision: October 2 1999 
-- Designer: Vincenzo Liguori 
-- Created by Xentec Inc. 
-- Copyright (c) 1995-1999 Xentec Inc. & Ocean Logic Pty Ltd 
-- Please review the terms of the license agreement before using this file. 
-- If you are not an authorized user, please destroy this source code file 
-- and notify Xentec, Inc. immediately that you inadvertently received an 
-- unauthorized copy. 1 888 7 XENTEC x22 
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mulv is port(
  idct : in std_logic;
  xin : in std_logic_vector(13 downto 0);
  y0, y1, y2, y3, y5, y6, y7 : out std_logic_vector(12 downto 0));
end mulv;

architecture rtl of mulv is
  signal x : std_logic_vector(14 downto 0);
  signal x3 : std_logic_vector(16 downto 0);
  signal x5, x7 : std_logic_vector(17 downto 0);
  signal x17 : std_logic_vector(19 downto 0);
  signal k7 : std_logic_vector(19 downto 0);
  signal k6 : std_logic_vector(20 downto 0);
  signal k5 : std_logic_vector(24 downto 0);
  signal k3 : std_logic_vector(25 downto 0);
  signal k2 : std_logic_vector(23 downto 0);
  signal k1 : std_logic_vector(25 downto 0);
  signal k0 : std_logic_vector(22 downto 0);
begin

  x <= xin(11 downto 0) & "000"  when idct = '1' else xin(13) & xin;
  
  x3 <= (x(14) & x & "0") + (x(14) & x(14) & x);
  x5 <= (x(14) & x & "00") + (x(14) & x(14) & x(14) & x);
  x7 <= (x & "000") - (x(14) & x(14) & x(14) & x);
  x17 <= (x(14) & x & "0000") + (x(14) & x(14) & x(14) & x(14) & x(14) & x);
  
  k7 <= x17 + (x(14) & x(14) &  x & "000");
  k6 <= (x17(19) & x17) + (x(14) &  x & "00000");
  k5 <= (k7(19) & k7(19) & k7(19) & k7(19) & k7(19) & k7) + (x17 & "00000");
  k3 <= (x7(17) & x7(17) & x7(17) & x7(17) & x7(17) & x7(17) & x7(17) & x7(17) & x7) + (x5(17) & x5(17) & x5(17) & x5 & "00000") + (x3 & "000000000");
  k2 <= (k7(19) & k7(19) & k7(19) & k7(19) & k7) + (x7 & "000000");
  k1 <= (k7(19) & k7(19) & k7(19) & k7(19) & k7(19) & k7(19) & k7) + (x3(16) & x3(16) & x3(16) & x3 & "000000") +(x7 & "00000000");
  k0 <= (x(14) & x(14) & x(14) & x(14) & x(14) & x(14) & x(14) & x(14) & x) + (x5(17) & x5(17) & x5(17) & x5 & "00") + (x5 & "00000");
  
  y0 <= k0(22 downto 10);
  y1 <= k1(25 downto 13);
  y2 <= k2(23 downto 11);
  y3 <= k3(25 downto 13);
  y5 <= k5(24 downto 12);
  y6 <= (k6(20) & k6(20 downto 9));
  y7 <= (k7(19) & k7(19) & k7(19 downto 9));

end rtl;