addr_gen.vhd

这是用VHDL语言(硬件描述语言)写的一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT).全同步设计,低门数.可以用于多媒体及打印应用领域.

---------------------------------------------------------------------------
-- Project: DCT 
-- Revision: 1.0 
-- Date of last Revision: October 2 1999 
-- Designer: Vincenzo Liguori 
-- Created by Xentec Inc. 
-- Copyright (c) 1995-1999 Xentec Inc. & Ocean Logic Pty Ltd 
-- Please review the terms of the license agreement before using this file. 
-- If you are not an authorized user, please destroy this source code file 
-- and notify Xentec, Inc. immediately that you inadvertently received an 
-- unauthorized copy. 1 888 7 XENTEC x22 
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity addr_gen is port(
  -- Inputs
  clk, res_n : in std_logic;
  start, en, idct : in std_logic;
  -- Outputs
  sgn1, sgn2, sgn3, sgn4, sgn5, sgn6, sgn7 : out std_logic;
  load, slx2, sli0, sli1, sli2 : out std_logic;
  slx40, slx41, slx42, slx43 : out std_logic_vector(1 downto 0);
  memh, memv : out std_logic_vector(5 downto 0);
  ready : out std_logic 
);
end addr_gen;

architecture rtl of addr_gen is
  signal ctrl : std_logic_vector(18 downto 0);
  signal index : std_logic_vector(2 downto 0);
  signal fliph, flipv : std_logic;
  signal ahh3, ahl3, avh3, avl3 : std_logic;
  signal ahh, ahl, avh, avl : std_logic_vector(2 downto 0);  
  signal rdy, mask : std_logic;
  signal slct : std_logic_vector(3 downto 0);
  signal memhi : std_logic_vector(5 downto 0);
begin

  rdy <= '1' when memhi = "000000" else '0';  
  ready <= rdy and mask;
  
  load <= '1' when index = "000" else '0';
  
  ahh3 <= '1' when ahh = "111" else '0';
  ahl3 <= '1' when ahl = "111" else '0';
  avh3 <= '1' when avh = "111" else '0';
  avl3 <= '1' when avl = "111" else '0';
  
  process(clk, res_n) begin
    if res_n = '0' then
      index <= (others => '0');
      fliph <= '0';
      flipv <= '0';
      ahh <= (others => '0');
      ahl <= (others => '0');
      avh <= (others => '0');
      avl <= (others => '0');
	mask <= '0';
    elsif clk = '1' and clk'event then
	if start = '1' then
        index <= (others => '0');
        fliph <= '1';
        flipv <= '0';
        ahh <= (others => '0');
        ahl <= "111";
        avh <= (others => '0');
        avl <= "001";
	  mask <= '0';
	elsif en = '1' then
	  if rdy = '1' then
	    mask <= '1';
	  end if;
	    
	  index <= index + '1';
	    
	  if (ahh3 and ahl3) = '1' then
	    fliph <= not fliph;
	  end if;
	    
	  if fliph = '0' then
	    ahl <= ahl + '1';
	    if ahl3 = '1' then
	      ahh <= ahh + '1';
	    end if;
	  else
	    ahh <= ahh + '1';
	    if ahh3 = '1' then
	      ahl <= ahl + '1';
	    end if;
	  end if;
	    
	  if (avh3 and avl3) = '1' then
	    flipv <= not flipv;
	  end if;
	    
	  if flipv = '0' then
	    avl <= avl + '1';
	    if avl3 = '1' then
            avh <= avh + '1';
          end if;
	  else
	    avh <= avh + '1';
	    if avh3 = '1' then
	      avl <= avl + '1';
	    end if;
	  end if;

      end if;
    end if;
  end process;
  
  memhi <= ahh & ahl;
  memh <= memhi;
  memv <= avh & avl;
  
  slct <= idct & index;
  process(slct) begin
    case slct is
      when "0000" => ctrl <= "0000000111001100011";
      when "0001" => ctrl <= "1111100111111000110";
      when "0010" => ctrl <= "0001110111100111001";
      when "0011" => ctrl <= "1100110111010011100";
      when "0100" => ctrl <= "0110011111010011100";
      when "0101" => ctrl <= "1011011111100111001";
      when "0110" => ctrl <= "0101001111111000110";
      when "0111" => ctrl <= "1010101111001100011";
      when "1000" => ctrl <= "0000000110000000000";
      when "1001" => ctrl <= "1111000111011100100";
      when "1010" => ctrl <= "0011110001001101001";
      when "1011" => ctrl <= "1000111111010001101";
      when "1100" => ctrl <= "0110011110000000000";
      when "1101" => ctrl <= "1011001111001110010";
      when "1110" => ctrl <= "0101101001010010110";
      when "1111" => ctrl <= "1010101111000011011";
      when others => ctrl <= (others => '0');
    end case;
  end process;
  
  sgn1 <= ctrl(12);
  sgn2 <= ctrl(13);
  sgn3 <= ctrl(14);
  sgn4 <= ctrl(15);
  sgn5 <= ctrl(16);
  sgn6 <= ctrl(17);
  sgn7 <= ctrl(18);
  
  sli0 <= ctrl(9);
  sli1 <= ctrl(10);
  sli2 <= ctrl(11);
  
  slx2 <= ctrl(8);
  
  slx40 <= ctrl(1 downto 0);
  slx41 <= ctrl(3 downto 2);
  slx42 <= ctrl(5 downto 4);
  slx43 <= ctrl(7 downto 6);
  
end rtl;