mulh.vhd

这是用VHDL语言(硬件描述语言)写的一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT).全同步设计,低门数.可以用于多媒体及打印应用领域.

---------------------------------------------------------------------------
-- Project: DCT 
-- Revision: 1.0 
-- Date of last Revision: October 2 1999 
-- Designer: Vincenzo Liguori 
-- Created by Xentec Inc. 
-- Copyright (c) 1995-1999 Xentec Inc. & Ocean Logic Pty Ltd 
-- Please review the terms of the license agreement before using this file. 
-- If you are not an authorized user, please destroy this source code file 
-- and notify Xentec, Inc. immediately that you inadvertently received an 
-- unauthorized copy. 1 888 7 XENTEC x22 
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mulh is port(
    clk, res_n : std_logic;
    en, idct : in std_logic;
    xin : in std_logic_vector(10 downto 0);
    y0, y1, y2, y3, y5, y6, y7 : out std_logic_vector(12 downto 0));
end mulh;

architecture rtl of mulh is
  signal x : std_logic_vector(10 downto 0);
  signal x3 : std_logic_vector(12 downto 0);
  signal x5, x7 : std_logic_vector(13 downto 0);
  signal x17 : std_logic_vector(15 downto 0);
  signal k7 : std_logic_vector(15 downto 0);
  signal k6 : std_logic_vector(16 downto 0);
  signal k5 : std_logic_vector(20 downto 0);
  signal k3 : std_logic_vector(21 downto 0);
  signal k2 : std_logic_vector(19 downto 0);
  signal k1 : std_logic_vector(21 downto 0);
  signal k0 : std_logic_vector(18 downto 0);
begin

  process(clk,res_n) begin
    if res_n = '0' then
      x <= (others => '0');
    elsif clk = '1' and clk'event then
      if en = '1' then
        if idct = '1' then
          x <= xin;
        else
          x <= xin(8 downto 0) & "00";
        end if;
      end if;
    end if;
  end process;
  
  x3 <= (x(10) & x & "0") + (x(10) & x(10) & x);
  x5 <= (x(10) & x & "00") + (x(10) & x(10) & x(10) & x);
  x7 <= (x & "000") - (x(10) & x(10) & x(10) & x);
  x17 <= (x(10) & x & "0000") + (x(10) & x(10) & x(10) & x(10) & x(10) & x);
  
  k7 <= x17 + (x(10) & x(10) &  x & "000");
  k6 <= (x17(15) & x17) + (x(10) &  x & "00000");
  k5 <= (k7(15) & k7(15) & k7(15) & k7(15) & k7(15) & k7) + (x17 & "00000");
  k3 <= (x7(13) & x7(13) & x7(13) & x7(13) & x7(13) & x7(13) & x7(13) & x7(13) & x7) + (x5(13) & x5(13) & x5(13) & x5 & "00000") + (x3 & "000000000");
  k2 <= (k7(15) & k7(15) & k7(15) & k7(15) & k7) + (x7 & "000000");
  k1 <= (k7(15) & k7(15) & k7(15) & k7(15) & k7(15) & k7(15) & k7) + (x3(12) & x3(12) & x3(12) & x3 & "000000") +(x7 & "00000000");
  k0 <= (x(10) & x(10) & x(10) & x(10) & x(10) & x(10) & x(10) & x(10) & x) + (x5(13) & x5(13) & x5(13) & x5 & "00") + (x5 & "00000");
  
  y0 <= k0(18 downto 6);
  y1 <= k1(21 downto 9);
  y2 <= k2(19 downto 7);
  y3 <= k3(21 downto 9);
  y5 <= k5(20 downto 8);
  y6 <= (k6(16) & k6(16 downto 5));
  y7 <= (k7(15) & k7(15) & k7(15 downto 5));
end rtl;