accv.vhd

这是用VHDL语言(硬件描述语言)写的一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT).全同步设计,低门数.可以用于多媒体及打印应用领域.

---------------------------------------------------------------------------
-- Project: DCT 
-- Revision: 1.0 
-- Date of last Revision: October 2 1999 
-- Designer: Vincenzo Liguori 
-- Created by Xentec Inc. 
-- Copyright (c) 1995-1999 Xentec Inc. & Ocean Logic Pty Ltd 
-- Please review the terms of the license agreement before using this file. 
-- If you are not an authorized user, please destroy this source code file 
-- and notify Xentec, Inc. immediately that you inadvertently received an 
-- unauthorized copy. 1 888 7 XENTEC x22 
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity accv is port(
  clk, res_n : in std_logic;
  en : in std_logic;
  sgn1, sgn2, sgn3, sgn4, sgn5, sgn6, sgn7, load : in std_logic;
  sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7 : in std_logic_vector(12 downto 0);
  y : out std_logic_vector(11 downto 0));
end accv;

architecture rtl of accv is
  signal reg0, reg1, reg2,  reg3, reg4, reg5, reg6, reg7 : std_logic_vector(12 downto 0);
  signal sh1, sh2, sh3, sh4, sh5, sh6, sh7 : std_logic_vector(11 downto 0);
  signal a0, a1, a2, a3, a4, a5, a6, a7 : std_logic_vector(12 downto 0);
  signal bx1, bx2, bx3, bx4, bx5, bx6, bx7 : std_logic_vector(12 downto 0);
  signal b0, b1, b2, b3, b4, b5, b6, b7 : std_logic_vector(13 downto 0);
begin

  a0 <= (others => '0') when load = '1' else reg0;
  a1 <= (others => '0') when load = '1' else reg1;
  a2 <= (others => '0') when load = '1' else reg2;
  a3 <= (others => '0') when load = '1' else reg3;
  a4 <= (others => '0') when load = '1' else reg4;
  a5 <= (others => '0') when load = '1' else reg5;
  a6 <= (others => '0') when load = '1' else reg6;
  a7 <= (others => '0') when load = '1' else reg7;
  
  bx1 <= not sel1 when sgn1 = '1' else sel1;
  bx2 <= not sel2 when sgn2 = '1' else sel2;
  bx3 <= not sel3 when sgn3 = '1' else sel3;
  bx4 <= not sel4 when sgn4 = '1' else sel4;
  bx5 <= not sel5 when sgn5 = '1' else sel5;
  bx6 <= not sel6 when sgn6 = '1' else sel6;
  bx7 <= not sel7 when sgn7 = '1' else sel7;

  b0 <= sel0(12) &  sel0;  
  b1 <= bx1(12) & bx1;
  b2 <= bx2(12) & bx2;
  b3 <= bx3(12) & bx3;
  b4 <= bx4(12) & bx4;
  b5 <= bx5(12) & bx5;
  b6 <= bx6(12) & bx6;
  b7 <= bx7(12) & bx7;
  
  process(clk,res_n) begin
    if res_n = '0' then
      reg0 <= (others => '0');
      reg1 <= (others => '0');
      reg2 <= (others => '0');
      reg3 <= (others => '0');
      reg4 <= (others => '0');
      reg5 <= (others => '0');
      reg6 <= (others => '0');
      reg7 <= (others => '0');
      sh1 <= (others => '0');
      sh2 <= (others => '0');      
      sh3 <= (others => '0');      
      sh4 <= (others => '0');      
      sh5 <= (others => '0');      
      sh6 <= (others => '0');      
      sh7 <= (others => '0');      
    elsif clk = '1' and clk'event then
      if en = '1' then
        reg0 <= a0 + b0(13 downto 1) + b0(0);
        reg1 <= a1 + b1(13 downto 1) + b1(0);
        reg2 <= a2 + b2(13 downto 1) + b2(0);
        reg3 <= a3 + b3(13 downto 1) + b3(0);
        reg4 <= a4 + b4(13 downto 1) + b4(0);
        reg5 <= a5 + b5(13 downto 1) + b5(0);
        reg6 <= a6 + b6(13 downto 1) + b6(0);
        reg7 <= a7 + b7(13 downto 1) + b7(0);
        
        if load ='1' then
          sh1 <= reg1(12 downto 1);
          sh2 <= reg2(12 downto 1);
          sh3 <= reg3(12 downto 1);
          sh4 <= reg4(12 downto 1);
          sh5 <= reg5(12 downto 1);
          sh6 <= reg6(12 downto 1);
          sh7 <= reg7(12 downto 1);
        else
          sh1 <= sh2;
          sh2 <= sh3;
          sh3 <= sh4;
          sh4 <= sh5;
          sh5 <= sh6;
          sh6 <= sh7;
        end if;
      end if;
    end if;
  end process;
  
  y <= reg0(12 downto 1) when load = '1' else sh1;
end rtl;