tb.vhd

这是用VHDL语言(硬件描述语言)写的一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT).全同步设计,低门数.可以用于多媒体及打印应用领域.

---------------------------------------------------------------------------
-- Project: DCT 
-- Revision: 1.0 
-- Date of last Revision: October 2 1999 
-- Designer: Vincenzo Liguori 
-- Created by Xentec Inc. 
-- Copyright (c) 1995-1999 Xentec Inc. & Ocean Logic Pty Ltd 
-- Please review the terms of the license agreement before using this file. 
-- If you are not an authorized user, please destroy this source code file 
-- and notify Xentec, Inc. immediately that you inadvertently received an 
-- unauthorized copy. 1 888 7 XENTEC x22 
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;

entity tb is
end tb;

architecture beh of tb is

file dcf : text is out "./dat/dct.dat";
file idcf : text is out "./dat/idct.dat";

component dct port(
  -- Inputs
  clk, res_n : in std_logic;
  start, en, idct : in std_logic;
  xh : in std_logic_vector(10 downto 0);
  xv : in std_logic_vector(13 downto 0);
  -- Outputs
  yh : out std_logic_vector(13 downto 0);
  yv : out std_logic_vector(11 downto 0);
  memh, memv : out std_logic_vector(5 downto 0);
  ready : out std_logic );
end component;

component dctram port(
  clk, en : in std_logic;
  ar, aw : in std_logic_vector(5 downto 0);
  din : in std_logic_vector(13 downto 0);
  dout : out std_logic_vector(13 downto 0));
end component;

  function to_char(v : std_logic_vector(3 downto 0)) return character is
  begin
    case v is
      when "0000" => return '0';
      when "0001" => return '1';
      when "0010" => return '2';
      when "0011" => return '3';
      when "0100" => return '4';
      when "0101" => return '5';
      when "0110" => return '6';
      when "0111" => return '7';
      when "1000" => return '8';
      when "1001" => return '9';
      when "1010" => return 'A';
      when "1011" => return 'B';
      when "1100" => return 'C';
      when "1101" => return 'D';
      when "1110" => return 'E';
      when "1111" => return 'F';
      when others => return 'X';
    end case;
  end to_char;

constant TCLK : time := 10 ns;
signal gnd : std_logic:='0';
signal vcc : std_logic:='1';
signal clk, rstn : std_logic:='1';
signal start, en, istart : std_logic;
signal rnd : std_logic_vector(30 downto 0);

signal xh, yi : std_logic_vector(10 downto 0);
signal yh, xv : std_logic_vector(13 downto 0);
signal yv : std_logic_vector(11 downto 0);
signal memh, memv : std_logic_vector(5 downto 0);
signal ready : std_logic;

signal iyh, ixv : std_logic_vector(13 downto 0);
signal iyv : std_logic_vector(11 downto 0);
signal iyout : std_logic_vector(8 downto 0);
signal imemh, imemv : std_logic_vector(5 downto 0);
signal iready : std_logic;

begin

  process begin -- Clock generator
    wait for TCLK/2;
    clk <= not clk;
  end process;

  process begin
    en <= '1';
    rstn <= '1';
    start <= '0';
    wait for TCLK/2;

    rstn <= '0';
    wait for TCLK;

    rstn <= '1';
    wait for TCLK + TCLK/2 + 1 ns;

    start <= '1';
    wait for TCLK;

    start <= '0';
    wait for 8* TCLK;

    istart <= '1';
    wait for TCLK;

    istart <= '0';
    wait;

  end process;

  -- Random number generator
  process(clk,rstn) begin
    if rstn = '0' then
      rnd <= "0000000100010110110000011000110";
    elsif clk = '1' and clk'event then
      if en = '1' then
        rnd <= rnd(29 downto 0) & (not (rnd(30) xor rnd(27)));
      end if;
    end if;
  end process;

  -- Level shifting;
  xh <= ("000" & rnd(7 downto 0)) - "00010000000";

  -- DCT module
dc : dct port map(
  clk => clk,
  res_n => rstn,
  start => start,
  en => en,
  idct => gnd,
  xh => xh,
  xv => xv,
  yh => yh,
  yv => yv,
  memh => memh,
  memv => memv,
  ready => ready
);

  -- Possible rounding for the DCT output
  yi <= yv(11 downto 1) + yv(0);

  -- Dual port DCT RAM
dr : dctram port map(
  clk => clk,
  en => en,
  ar => memv,
  aw => memh,
  din => yh,
  dout => xv
);

  -- IDCT module
idc : dct port map(
  clk => clk,
  res_n => rstn,
  start => istart,
  en => en,
  idct => vcc,
  xh => yi,
  xv => ixv,
  yh => iyh,
  yv => iyv,
  memh => imemh,
  memv => imemv,
  ready => iready
);

  -- A possible rounding for the IDCT output
  iyout <= iyv(10 downto 2) + iyv(1);

idr : dctram port map(
  clk => clk,
  en => en,
  ar => imemv,
  aw => imemh,
  din => iyh,
  dout => ixv
);

  -- Storage of DCT output
  process
    variable tline : line;
  begin

    loop
      wait until clk'event and clk = '1';
      if ready = '1' then
        exit;
      end if;
    end loop;

    write(tline,to_char(("0" & yi(10 downto 8))));
    write(tline,to_char(yi(7 downto 4)));
    write(tline,to_char(yi(3 downto 0)));
    writeline(dcf,tline);
    for i in 0 to 126 loop -- Store 128 DCT outputs
      wait until clk'event and clk = '1';
      write(tline,to_char(("0" & yi(10 downto 8))));
      write(tline,to_char(yi(7 downto 4)));
      write(tline,to_char(yi(3 downto 0)));
      writeline(dcf,tline);
    end loop;

    wait;
  end process;

  -- Storage of IDCT output
  process
    variable tline : line;
  begin

    loop
      wait until clk'event and clk = '1';
      if ready = '1' then
        exit;
      end if;
    end loop;

    for i in 0 to 1 loop
      loop
        wait until clk'event and clk = '1';
        if iready = '1' then
          exit;
        end if;
      end loop;
    end loop;

    write(tline,to_char(("000" & iyout(8))));
    write(tline,to_char(iyout(7 downto 4)));
    write(tline,to_char(iyout(3 downto 0)));
    writeline(idcf,tline);
    for i in 0 to 126 loop -- Store 128 IDCT outputs
      wait until clk'event and clk = '1';
      write(tline,to_char(("000" & iyout(8))));
      write(tline,to_char(iyout(7 downto 4)));
      write(tline,to_char(iyout(3 downto 0)));
      writeline(idcf,tline);
    end loop;

    assert(false) report "End of tb" severity failure;

    wait;
  end process;


end beh;