dctram.vhd

这是用VHDL语言(硬件描述语言)写的一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT).全同步设计,低门数.可以用于多媒体及打印应用领域.

---------------------------------------------------------------------------
-- Project: DCT 
-- Revision: 1.0 
-- Date of last Revision: October 2 1999 
-- Designer: Vincenzo Liguori 
-- Created by Xentec Inc. 
-- Copyright (c) 1995-1999 Xentec Inc. & Ocean Logic Pty Ltd 
-- Please review the terms of the license agreement before using this file. 
-- If you are not an authorized user, please destroy this source code file 
-- and notify Xentec, Inc. immediately that you inadvertently received an 
-- unauthorized copy. 1 888 7 XENTEC x22 
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dctram is port(
  -- Inputs
  clk, en : in std_logic;
  ar, aw : in std_logic_vector(5 downto 0);
  din : in std_logic_vector(13 downto 0);
  -- Outputs
  dout : out std_logic_vector(13 downto 0)
);
end dctram;

architecture beh of dctram is
  type dram is array (63 downto 0) of std_logic_vector(13 downto 0);
  signal mem : dram;
begin

  process(clk) begin
    if en = '1' then
      if clk'event and clk = '1' then
        -- Write port
        mem(conv_integer(aw)) <= din;
        -- Read port
        dout <= mem(conv_integer(ar));
      end if;
    end if;
  end process;
  
end beh;