📄 md_tb.vhd

📁 这是一个曼彻斯特编解码的VHDL源代码
💻 VHD
字号:
--  Manchester decoder test bench--  Xilinx, Inc--  Jan 26, 2000library ieee ;use ieee.std_logic_1164.all ;entity testbench is end ;architecture v1 of testbench is component mdport (rst : in std_logic ;	clk16x : in std_logic ;	mdi : in std_logic ;	rdn : in std_logic ;	dout : out std_logic_vector (7 downto 0);	data_ready : out std_logic 	);end component ;signal rst : std_logic ;signal clk16x : std_logic ;signal mdi : std_logic ;signal rdn : std_logic ;signal dout : std_logic_vector (7 downto 0) ;signal data_ready : std_logic ;type test_record is recordrst : std_logic ;mdi : std_logic ;rdn : std_logic ;dout : std_logic_vector (7 downto 0) ;data_ready : std_logic ;end record ;type test_array is array(positive range<>) of test_record ;constant test_vectors : test_array := (('1','0','1',"00000000",'0'), -- 40('0','0','1',"10101010",'0'), -- 80('0','1','1',"10101010",'0'), -- 120('0','1','1',"10101010",'0'), -- 160('0','1','1',"10101010",'0'), -- 200('0','1','1',"10101010",'0'), -- 240('0','1','1',"10101010",'0'), -- 280('0','1','1',"10101010",'0'), -- 320('0','1','1',"10101010",'0'), -- 360('0','1','1',"10101010",'0'), -- 400('0','0','1',"10101010",'0'), -- 440('0','0','1',"10101010",'0'), -- 480('0','0','1',"10101010",'0'), -- 520('0','0','1',"10101010",'0'), -- 560('0','0','1',"11111111",'0'), -- 600('0','0','1',"11111111",'0'), -- 640('0','0','1',"11111111",'0'), -- 680('0','0','1',"11111111",'0'), -- 680('0','1','1',"11111111",'0'), -- 880('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- 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('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','0','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0'), -- ('0','1','1',"11111111",'0')	) ;beginuut : md port map (rst,clk16x,mdi,rdn,dout,data_ready) ;process	variable vector : test_record ;begin	for index in test_vectors'range loop	vector := test_vectors(index);	rst <= vector.rst ;	mdi <= vector.mdi ;	rdn <= vector.rdn ;	dout <= vector.dout ;	data_ready <= vector.data_ready ;		clk16x <= '0' ;	wait for 20 ns ;	clk16x <= '1' ;	wait for 20 ns ;	clk16x <= '0' ;assert dout = test_vectors(index).dout report "Output dout is incorrect." severity note ;assert data_ready = test_vectors(index).data_ready report "Output data_ready is incorrect." severity note ;end loop ;wait ;	end process ;end ;
💿 文件大小 11 K
👤 上传用户 a6810121
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#VHDL #曼彻斯特 #编解码 #源代码
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