fdivision1.rpt

出租车计价器

-- Equation name is '_LC1_H6', type is buried 
_LC1_H6  = LCELL( _EQ024);
  _EQ024 =  i0 &  i1;

-- Node name is '|lpm_add_sub:221|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_H13', type is buried 
_LC3_H13 = LCELL( _EQ025);
  _EQ025 =  i2 &  i3 &  _LC1_H6;

-- Node name is '|lpm_add_sub:221|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_H13', type is buried 
_LC4_H13 = LCELL( _EQ026);
  _EQ026 =  i4 &  _LC3_H13;

-- Node name is '|lpm_add_sub:221|addcore:adder|:155' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_H13', type is buried 
_LC2_H13 = LCELL( _EQ027);
  _EQ027 =  i5 &  i6 &  _LC4_H13;

-- Node name is '|lpm_add_sub:221|addcore:adder|:159' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_H16', type is buried 
_LC4_H16 = LCELL( _EQ028);
  _EQ028 =  i7 &  _LC2_H13;

-- Node name is '|lpm_add_sub:221|addcore:adder|:167' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_H20', type is buried 
_LC2_H20 = LCELL( _EQ029);
  _EQ029 =  i7 &  i8 &  i9 &  _LC2_H13;

-- Node name is '|lpm_add_sub:221|addcore:adder|:171' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_H20', type is buried 
_LC5_H20 = LCELL( _EQ030);
  _EQ030 =  i10 &  _LC2_H20;

-- Node name is '|lpm_add_sub:221|addcore:adder|:179' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_H20', type is buried 
_LC4_H20 = LCELL( _EQ031);
  _EQ031 =  i11 &  i12 &  _LC5_H20;

-- Node name is '|lpm_add_sub:221|addcore:adder|:183' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_H6', type is buried 
_LC7_H6  = LCELL( _EQ032);
  _EQ032 =  i13 &  _LC4_H20;

-- Node name is '|lpm_add_sub:221|addcore:adder|:191' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_H26', type is buried 
_LC4_H26 = LCELL( _EQ033);
  _EQ033 =  i13 &  i14 &  i15 &  _LC4_H20;

-- Node name is '|lpm_add_sub:221|addcore:adder|:199' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_H26', type is buried 
_LC5_H26 = LCELL( _EQ034);
  _EQ034 =  i16 &  i17 &  _LC4_H26;

-- Node name is '|lpm_add_sub:221|addcore:adder|:203' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_H26', type is buried 
_LC2_H26 = LCELL( _EQ035);
  _EQ035 =  i16 &  i17 &  i18 &  _LC4_H26;

-- Node name is '|lpm_add_sub:221|addcore:adder|:211' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_H11', type is buried 
_LC3_H11 = LCELL( _EQ036);
  _EQ036 =  i19 &  i20 &  _LC2_H26;

-- Node name is '|lpm_add_sub:221|addcore:adder|:215' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_H11', type is buried 
_LC4_H11 = LCELL( _EQ037);
  _EQ037 =  i21 &  _LC3_H11;

-- Node name is '~114~1' 
-- Equation name is '~114~1', location is LC1_H20, type is buried.
-- synthesized logic cell 
!_LC1_H20 = _LC1_H20~NOT;
_LC1_H20~NOT = LCELL( _EQ038);
  _EQ038 = !i12 & !i13 &  i14 & !i15;

-- Node name is '~114~2' 
-- Equation name is '~114~2', location is LC1_H26, type is buried.
-- synthesized logic cell 
!_LC1_H26 = _LC1_H26~NOT;
_LC1_H26~NOT = LCELL( _EQ039);
  _EQ039 = !i16 & !i17 & !i18 & !i19;

-- Node name is '~114~3' 
-- Equation name is '~114~3', location is LC2_H11, type is buried.
-- synthesized logic cell 
!_LC2_H11 = _LC2_H11~NOT;
_LC2_H11~NOT = LCELL( _EQ040);
  _EQ040 = !i21 & !i22 & !i23;

-- Node name is '~114~4' 
-- Equation name is '~114~4', location is LC1_H11, type is buried.
-- synthesized logic cell 
!_LC1_H11 = _LC1_H11~NOT;
_LC1_H11~NOT = LCELL( _EQ041);
  _EQ041 = !i20 & !_LC1_H20 & !_LC1_H26 & !_LC2_H11;

-- Node name is '~114~5' 
-- Equation name is '~114~5', location is LC5_H13, type is buried.
-- synthesized logic cell 
!_LC5_H13 = _LC5_H13~NOT;
_LC5_H13~NOT = LCELL( _EQ042);
  _EQ042 = !i5 & !i6 & !i7;

-- Node name is '~114~6' 
-- Equation name is '~114~6', location is LC3_H20, type is buried.
-- synthesized logic cell 
!_LC3_H20 = _LC3_H20~NOT;
_LC3_H20~NOT = LCELL( _EQ043);
  _EQ043 = !i8 &  i9 &  i10 &  i11;

-- Node name is ':114' 
-- Equation name is '_LC1_H13', type is buried 
_LC1_H13 = LCELL( _EQ044);
  _EQ044 = !_LC1_H11 & !_LC3_H20 &  _LC4_H13 & !_LC5_H13;

-- Node name is ':218' 
-- Equation name is '_LC8_H16', type is buried 
_LC8_H16 = DFFE(!_LC8_H16, GLOBAL( F40M),  VCC,  VCC,  _LC1_H13);



Project Information                               f:\论文\taxi1\fdivision1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:05
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:08


Memory Allocated
-----------------

Peak memory allocated during compilation  = 51,067K