📄 ntaxi.rpt
字号:
B32 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 5/26( 19%)
B33 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 6/26( 23%)
B37 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 5/26( 19%)
B43 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 12/26( 46%)
B45 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 3/26( 11%)
B47 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/26( 15%)
B52 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 4/26( 15%)
D28 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 5/26( 19%)
D30 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 4/26( 15%)
D39 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 3/26( 11%)
D44 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 0/2 10/26( 38%)
F27 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 9/26( 34%)
F37 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/26( 23%)
F39 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 4/26( 15%)
F40 8/ 8(100%) 6/ 8( 75%) 2/ 8( 25%) 1/2 0/2 9/26( 34%)
F45 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 5/26( 19%)
F46 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 0/2 8/26( 30%)
F49 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 4/26( 15%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 3/6 ( 50%)
Total I/O pins used: 33/141 ( 23%)
Total logic cells used: 156/4992 ( 3%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
Average fan-in: 3.49/4 ( 87%)
Total fan-in: 545/19968 ( 2%)
Total input pins required: 3
Total input I/O cell registers required: 0
Total output pins required: 33
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 156
Total flipflops required: 66
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 30/4992 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 1 0 17/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 0 0 8 0 0 0 0 0 8 0 8 0 8 0 0 0 0 8 56/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 0 0 0 0 0 0 0 0 8 0 0 0 0 8 0 0 0 0 0 0 0 0 32/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 8 0 8 8 0 0 0 0 3 8 0 0 8 0 0 0 51/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 8 0 16 8 0 0 0 16 0 16 8 0 0 8 8 11 16 8 0 8 0 1 8 156/0
Device-Specific Information: f:\论文\taxi1\ntaxi.rpt
ntaxi
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G ^ 0 0 0 0 clk
183 - - - -- INPUT G ^ 0 0 0 0 flag
78 - - - -- INPUT ^ 0 0 0 51 reset
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\论文\taxi1\ntaxi.rpt
ntaxi
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
60 - - - 40 OUTPUT 0 1 0 0 c10
36 - - H -- OUTPUT 0 1 0 0 c11
29 - - G -- OUTPUT 0 1 0 0 c12
200 - - - 46 OUTPUT 0 1 0 0 c13
187 - - - 28 OUTPUT 0 1 0 0 c20
127 - - F -- OUTPUT 0 1 0 0 c21
126 - - F -- OUTPUT 0 1 0 0 c22
75 - - - 27 OUTPUT 0 1 0 0 c23
186 - - - 27 OUTPUT 0 1 0 0 c30
195 - - - 39 OUTPUT 0 1 0 0 c31
61 - - - 40 OUTPUT 0 1 0 0 c32
56 - - - 45 OUTPUT 0 1 0 0 c33
8 - - A -- OUTPUT 0 1 0 0 c40
9 - - A -- OUTPUT 0 1 0 0 c41
7 - - A -- OUTPUT 0 1 0 0 c42
125 - - F -- OUTPUT 0 1 0 0 c43
208 - - - 52 OUTPUT 0 1 0 0 ifw
15 - - C -- OUTPUT 0 1 0 0 m10
142 - - B -- OUTPUT 0 1 0 0 m11
143 - - B -- OUTPUT 0 1 0 0 m12
11 - - B -- OUTPUT 0 1 0 0 m13
13 - - B -- OUTPUT 0 1 0 0 m20
147 - - B -- OUTPUT 0 1 0 0 m21
12 - - B -- OUTPUT 0 1 0 0 m22
31 - - H -- OUTPUT 0 1 0 0 m23
135 - - D -- OUTPUT 0 1 0 0 w10
17 - - D -- OUTPUT 0 1 0 0 w11
133 - - D -- OUTPUT 0 1 0 0 w12
47 - - L -- OUTPUT 0 1 0 0 w13
19 - - D -- OUTPUT 0 1 0 0 w20
18 - - D -- OUTPUT 0 1 0 0 w21
134 - - D -- OUTPUT 0 1 0 0 w22
16 - - D -- OUTPUT 0 1 0 0 w23
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\论文\taxi1\ntaxi.rpt
ntaxi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 45 AND2 0 2 0 4 |lpm_add_sub:1169|addcore:adder|:67
- 6 - B 45 AND2 0 2 0 1 |lpm_add_sub:1169|addcore:adder|:71
- 3 - B 45 AND2 0 3 0 3 |lpm_add_sub:1169|addcore:adder|:75
- 6 - B 33 AND2 0 2 0 1 |lpm_add_sub:1169|addcore:adder|:79
- 5 - B 43 AND2 0 2 0 1 |lpm_add_sub:1171|addcore:adder|:55
- 7 - B 32 AND2 0 3 0 1 |lpm_add_sub:1171|addcore:adder|:59
- 5 - B 47 OR2 ! 0 2 0 4 |lpm_add_sub:1172|addcore:adder|:63
- 2 - B 37 AND2 0 3 0 2 |lpm_add_sub:1172|addcore:adder|:71
- 7 - F 39 AND2 0 2 0 1 |lpm_add_sub:1174|addcore:adder|:55
- 2 - F 49 AND2 0 3 0 1 |lpm_add_sub:1175|addcore:adder|:59
- 7 - F 49 OR2 0 3 0 1 |lpm_add_sub:1175|addcore:adder|:68
- 1 - F 37 AND2 0 2 0 3 |lpm_add_sub:1176|addcore:adder|:55
- 8 - A 46 OR2 ! 0 2 0 4 |lpm_add_sub:1177|addcore:adder|:55
- 5 - D 30 AND2 0 2 0 1 |lpm_add_sub:1178|addcore:adder|:55
- 7 - D 28 AND2 0 3 0 1 |lpm_add_sub:1179|addcore:adder|:59
- 4 - D 44 OR2 0 3 0 1 |lpm_add_sub:1179|addcore:adder|:68
- 2 - A 51 DFFE + 0 0 1 17 :39
- 4 - B 33 OR2 s 0 2 0 1 ~97~1
- 1 - B 33 OR2 ! 0 4 0 10 :97
- 2 - B 33 AND2 ! 0 3 0 4 :117
- 1 - B 45 OR2 ! 0 3 0 2 :124
- 7 - B 33 OR2 0 4 0 1 :164
- 3 - B 33 OR2 0 4 0 1 :165
- 3 - B 43 AND2 s 1 1 0 7 ~218~1
- 7 - B 43 AND2 s ! 0 2 0 4 ~218~2
- 8 - B 33 DFFE + 0 3 0 3 tempm6 (:228)
- 5 - B 33 DFFE + 0 3 0 4 tempm5 (:229)
- 4 - B 45 DFFE + 0 3 0 3 tempm4 (:230)
- 7 - B 45 DFFE + 0 3 0 2 tempm3 (:231)
- 5 - B 45 DFFE + 0 3 0 3 tempm2 (:232)
- 8 - B 45 DFFE + 0 3 0 1 tempm1 (:233)
- 2 - B 43 DFFE + 0 3 0 2 tempm0 (:234)
- 2 - B 52 AND2 0 4 0 6 :239
- 6 - B 32 AND2 s 0 2 0 3 ~256~1
- 7 - B 52 OR2 0 4 0 1 :256
- 4 - B 52 OR2 0 3 0 1 :257
- 3 - B 52 OR2 0 3 0 1 :258
- 1 - B 52 DFFE + 1 2 1 3 :277
- 6 - B 52 DFFE + 1 2 1 4 :278
- 8 - B 52 DFFE + 1 2 1 3 :279
- 6 - F 40 DFFE + 1 1 1 3 :280
- 4 - B 32 OR2 s 0 4 0 3 ~298~1
- 2 - B 32 OR2 0 4 0 1 :307
- 6 - B 43 OR2 0 4 0 1 :308
- 5 - B 32 OR2 0 4 0 1 :309
- 8 - F 40 DFFE + 1 2 1 3 :332
- 4 - B 43 DFFE + 1 2 1 4 :333
- 1 - B 32 DFFE + 1 2 1 5 :334
- 8 - B 32 DFFE + 1 2 1 5 :335
- 5 - B 52 AND2 ! 0 2 0 3 :360
- 3 - B 32 OR2 s 0 2 0 1 ~396~1
- 8 - B 43 OR2 s 0 4 0 1 ~396~2
- 1 - B 43 OR2 0 4 0 16 :396
- 2 - D 39 OR2 s 0 3 0 1 ~427~1
- 4 - B 37 OR2 s 0 3 0 1 ~443~1
- 1 - B 37 OR2 ! 0 4 0 11 :443
- 3 - A 46 AND2 s 0 2 0 3 ~444~1
- 4 - A 32 AND2 s 0 2 0 1 ~444~2
- 7 - A 32 AND2 s 0 4 0 1 ~444~3
- 4 - F 37 AND2 s 0 3 0 2 ~444~4
- 7 - F 37 AND2 s 0 3 0 1 ~444~5
- 7 - D 44 OR2 ! 0 4 0 14 :444
- 3 - B 37 AND2 ! 0 4 0 6 :478
- 7 - B 37 OR2 0 4 0 1 :518
- 7 - B 47 OR2 0 3 0 1 :519
- 5 - B 37 OR2 0 4 0 1 :520
- 8 - B 47 OR2 0 3 0 1 :521
- 6 - D 44 AND2 s 1 1 0 4 ~579~1
- 2 - D 28 AND2 s 1 2 0 6 ~579~2
- 4 - B 47 AND2 s ! 0 2 0 1 ~583~1
- 8 - B 37 DFFE + 0 3 0 3 tempt5 (:591)
- 2 - B 47 DFFE + 0 3 0 4 tempt4 (:592)
- 6 - B 37 DFFE + 0 3 0 4 tempt3 (:593)
- 3 - B 47 DFFE + 0 3 0 5 tempt2 (:594)
- 6 - B 47 DFFE + 0 3 0 1 tempt1 (:595)
- 1 - B 47 DFFE + 0 3 0 2 tempt0 (:596)
- 8 - D 39 OR2 0 3 0 1 :611
- 1 - D 39 OR2 0 4 0 1 :637
- 3 - D 39 OR2 0 4 0 1 :638
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