sel.v

来自「出租车计价器」· Verilog 代码 · 共 71 行

module sel(in1,in2,in3,in4,in5,in6,in7,in8,clk1,ms1,ms2,ms3,ms4,ms5,ms6,ms7,ms8,a,b,c,d,e,f,g,p);
input clk1;
input[3:0]in1,in2,in3,in4,in5,in6,in7,in8;
output ms1,ms2,ms3,ms4,ms5,ms6,ms7,ms8,a,b,c,d,e,f,g,p;
reg ms1,ms2,ms3,ms4,ms5,ms6,ms7,ms8,a,b,c,d,e,f,g,p;
reg[3:0] temp,flag1;
always@(posedge clk1)
begin
{ms1,ms2,ms3,ms4,ms5,ms6,ms7,ms8}=8'b00000000;
flag1=flag1+1;
case(flag1)
  0:
    begin 
    temp=in1;
    ms1=1;  
    end
  1:
    begin 
    temp=in2;
    ms2=1;
    p=1;
    end
  2:
    begin 
    temp=in3;
    ms3=1; 
    end
  3:
    begin 
    temp=in4;
    ms4=1;
    end
  4:
    begin 
    temp=in5;
    ms5=1;
    end
  5:
    begin 
    temp=in6;
    ms6=1; 
    end
  6:
    begin 
    temp=in7;
    ms7=1;
    end
  7:
    begin 
    temp=in8;
    ms8=1;
    end
endcase
case(temp)
  4'd0:{a,b,c,d,e,f,g}=7'b1111110;
  4'd1:{a,b,c,d,e,f,g}=7'b0110000;
  4'd2:{a,b,c,d,e,f,g}=7'b1101101;
  4'd3:{a,b,c,d,e,f,g}=7'b1111001;
  4'd4:{a,b,c,d,e,f,g}=7'b0110011;
  4'd5:{a,b,c,d,e,f,g}=7'b1011011;
  4'd6:{a,b,c,d,e,f,g}=7'b1011111;
  4'd7:{a,b,c,d,e,f,g}=7'b1110000;
  4'd8:{a,b,c,d,e,f,g}=7'b1111111;
  4'd9:{a,b,c,d,e,f,g}=7'b1111011;
  default:{a,b,c,d,e,f,g}=7'b1111110;
endcase
end
endmodule