📄 sel3.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\论文\taxi1\sel3.rpt
sel3
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 13 DFFE + 0 3 0 17 flag13 (:54)
- 2 - A 15 DFFE + 0 2 0 18 flag12 (:55)
- 1 - A 15 DFFE + 0 1 0 19 flag11 (:56)
- 5 - A 15 DFFE + 0 0 0 20 flag10 (:57)
- 7 - A 24 AND2 0 4 0 14 :62
- 5 - A 24 DFFE + 0 4 1 0 :80
- 7 - A 13 AND2 0 4 0 14 :85
- 3 - A 24 DFFE + 0 4 1 0 :95
- 4 - A 24 AND2 0 4 0 14 :100
- 8 - A 13 DFFE + 0 4 1 0 :110
- 3 - A 15 AND2 0 4 0 14 :115
- 3 - A 13 DFFE + 0 4 1 0 :125
- 8 - A 24 AND2 0 4 0 13 :130
- 2 - A 13 DFFE + 0 4 1 0 :140
- 5 - A 13 AND2 0 4 0 13 :145
- 1 - A 24 DFFE + 0 4 1 0 :155
- 6 - A 15 AND2 0 4 0 13 :160
- 1 - A 13 DFFE + 0 4 1 0 :170
- 4 - A 13 AND2 0 4 0 13 :175
- 6 - A 24 DFFE + 0 4 1 0 :185
- 3 - C 04 AND2 s 0 3 0 1 ~224~1
- 2 - A 24 OR2 ! 0 4 0 13 :224
- 1 - C 06 OR2 s 2 2 0 1 ~262~1
- 2 - C 06 OR2 s 2 2 0 1 ~262~2
- 3 - C 06 OR2 s 1 2 0 1 ~262~3
- 5 - C 06 OR2 s 2 2 0 1 ~262~4
- 6 - C 06 OR2 s 1 3 0 1 ~262~5
- 4 - C 06 OR2 0 4 0 4 :262
- 3 - C 20 OR2 s 2 2 0 1 ~263~1
- 4 - C 20 OR2 s 2 2 0 1 ~263~2
- 6 - C 20 OR2 s 1 2 0 1 ~263~3
- 2 - C 24 OR2 s 2 2 0 1 ~263~4
- 8 - C 15 OR2 s 1 3 0 1 ~263~5
- 5 - C 20 OR2 0 4 0 5 :263
- 4 - C 18 OR2 s 2 2 0 1 ~264~1
- 1 - C 17 OR2 s 2 2 0 1 ~264~2
- 1 - C 05 OR2 s 1 2 0 1 ~264~3
- 2 - C 05 OR2 s 1 3 0 1 ~264~4
- 2 - C 13 OR2 s 2 2 0 1 ~264~5
- 6 - C 05 OR2 0 4 0 5 :264
- 4 - C 21 OR2 s 2 2 0 1 ~265~1
- 2 - C 04 OR2 s 2 2 0 1 ~265~2
- 8 - C 04 OR2 s 1 2 0 1 ~265~3
- 1 - C 02 OR2 s 1 3 0 1 ~265~4
- 2 - C 02 OR2 s 2 2 0 1 ~265~5
- 6 - C 02 OR2 0 4 0 6 :265
- 7 - C 06 DFFE + 0 1 0 8 temp3 (:266)
- 6 - C 12 DFFE + 0 1 0 7 temp2 (:267)
- 7 - C 22 DFFE + 0 1 0 7 temp1 (:268)
- 4 - C 02 DFFE + 0 1 0 6 temp0 (:269)
- 1 - C 16 AND2 s 4 0 0 1 ~278~1
- 4 - C 14 AND2 s 4 0 0 1 ~278~2
- 5 - C 14 AND2 s 2 1 0 1 ~278~3
- 2 - C 14 OR2 s 0 4 0 1 ~278~4
- 5 - C 16 OR2 s 2 2 0 1 ~278~5
- 1 - C 15 OR2 s 0 4 0 1 ~278~6
- 1 - C 19 AND2 s 4 0 0 1 ~278~7
- 6 - C 21 AND2 s 4 0 0 1 ~278~8
- 7 - C 21 OR2 s 0 4 0 1 ~278~9
- 3 - C 23 OR2 s 1 3 0 1 ~278~10
- 4 - C 15 AND2 s 0 4 0 1 ~278~11
- 5 - C 15 AND2 s 4 0 0 1 ~278~12
- 6 - C 15 OR2 s 0 4 0 1 ~278~13
- 5 - C 21 OR2 s 3 1 0 1 ~331~1
- 6 - C 16 OR2 s 3 0 0 1 ~331~2
- 5 - C 17 OR2 s 3 0 0 1 ~331~3
- 8 - C 16 OR2 s 0 4 0 1 ~331~4
- 3 - C 16 OR2 s 1 3 0 1 ~331~5
- 3 - C 14 OR2 s 3 1 0 1 ~331~6
- 6 - C 22 OR2 s 0 3 0 1 ~331~7
- 2 - C 19 OR2 s 3 0 0 1 ~331~8
- 5 - C 19 OR2 s 0 4 0 1 ~331~9
- 6 - C 19 OR2 s 1 3 0 1 ~331~10
- 7 - C 23 AND2 s ! 3 0 0 2 ~331~11
- 7 - C 19 OR2 s 0 4 0 1 ~331~12
- 4 - C 19 OR2 ! 0 4 0 4 :331
- 2 - C 23 OR2 s 3 1 0 1 ~384~1
- 6 - C 17 OR2 s 3 1 0 1 ~384~2
- 3 - C 12 OR2 s 0 4 0 1 ~384~3
- 6 - C 24 OR2 s 3 1 0 1 ~384~4
- 8 - C 14 OR2 s 3 1 0 1 ~384~5
- 7 - C 17 AND2 s 0 4 0 1 ~384~6
- 3 - C 15 OR2 s 3 1 0 1 ~384~7
- 2 - C 16 OR2 s 3 1 0 1 ~384~8
- 4 - C 16 OR2 s 3 1 0 1 ~384~9
- 3 - C 21 OR2 s 3 1 0 1 ~384~10
- 7 - C 16 AND2 s 0 4 0 1 ~384~11
- 2 - C 17 AND2 0 4 0 5 :384
- 7 - C 14 OR2 s 2 1 0 1 ~437~1
- 7 - C 20 OR2 s 2 2 0 1 ~437~2
- 1 - C 20 OR2 s 2 2 0 1 ~437~3
- 1 - C 24 OR2 s 2 2 0 1 ~437~4
- 3 - C 24 OR2 s 2 2 0 1 ~437~5
- 7 - C 15 OR2 s 0 3 0 1 ~437~6
- 4 - C 24 OR2 s 2 2 0 1 ~437~7
- 7 - C 24 OR2 s 2 2 0 1 ~437~8
- 8 - C 24 OR2 s 2 2 0 1 ~437~9
- 5 - C 24 AND2 0 4 0 4 :437
- 8 - C 23 OR2 s 3 1 0 1 ~490~1
- 2 - C 12 OR2 s 0 4 0 1 ~490~2
- 4 - C 12 OR2 s 3 1 0 1 ~490~3
- 6 - C 14 OR2 s 3 1 0 1 ~490~4
- 5 - C 12 OR2 s 3 1 0 1 ~490~5
- 7 - C 12 AND2 s ! 0 4 0 1 ~490~6
- 3 - C 17 OR2 s 3 1 0 1 ~490~7
- 7 - C 18 OR2 s 3 1 0 1 ~490~8
- 8 - C 18 OR2 s 3 1 0 1 ~490~9
- 8 - C 19 OR2 s 3 1 0 1 ~490~10
- 2 - C 18 AND2 s ! 0 4 0 1 ~490~11
- 1 - C 12 AND2 0 4 0 6 :490
- 3 - C 05 OR2 s 2 1 0 1 ~543~1
- 4 - C 05 OR2 s 0 4 0 1 ~543~2
- 5 - C 05 OR2 s 2 2 0 1 ~543~3
- 7 - C 05 OR2 s 2 2 0 1 ~543~4
- 8 - C 05 OR2 s 2 2 0 1 ~543~5
- 1 - C 18 OR2 s 2 1 0 1 ~543~6
- 3 - C 18 OR2 s 2 2 0 1 ~543~7
- 5 - C 18 OR2 s 2 2 0 1 ~543~8
- 6 - C 18 OR2 s 2 2 0 1 ~543~9
- 6 - C 09 AND2 0 4 0 2 :543
- 3 - C 02 OR2 s 0 3 0 1 ~596~1
- 5 - C 02 OR2 s 2 2 0 1 ~596~2
- 7 - C 02 OR2 s 2 2 0 1 ~596~3
- 8 - C 02 OR2 s 2 2 0 1 ~596~4
- 1 - C 23 OR2 s 2 2 0 1 ~596~5
- 4 - C 04 OR2 s 2 1 0 1 ~596~6
- 5 - C 04 OR2 s 2 2 0 1 ~596~7
- 6 - C 04 OR2 s 2 2 0 1 ~596~8
- 7 - C 04 OR2 s 2 2 0 1 ~596~9
- 3 - C 09 AND2 0 4 0 3 :596
- 5 - C 09 OR2 ! 0 4 0 4 :649
- 4 - C 23 OR2 s 3 1 0 1 ~702~1
- 4 - C 22 OR2 s 0 4 0 1 ~702~2
- 5 - C 22 OR2 s 1 2 0 1 ~702~3
- 1 - C 14 OR2 s 3 1 0 1 ~702~4
- 8 - C 22 OR2 s 3 1 0 1 ~702~5
- 3 - C 22 AND2 s 0 4 0 1 ~702~6
- 4 - C 17 OR2 s 3 1 0 1 ~702~7
- 1 - C 21 OR2 s 1 2 0 1 ~702~8
- 2 - C 21 OR2 s 3 1 0 1 ~702~9
- 3 - C 19 OR2 s 3 1 0 1 ~702~10
- 8 - C 21 AND2 s 0 4 0 1 ~702~11
- 5 - C 23 AND2 0 4 0 2 :702
- 2 - C 10 AND2 s 2 0 0 4 ~755~1
- 8 - C 17 OR2 s 2 1 0 1 ~755~2
- 1 - C 22 OR2 s 0 3 0 1 ~755~3
- 2 - C 22 OR2 s 0 4 0 1 ~755~4
- 3 - C 13 OR2 s 2 2 0 1 ~755~5
- 4 - C 13 OR2 s 2 2 0 1 ~755~6
- 2 - C 20 AND2 s 2 0 0 4 ~755~7
- 5 - C 13 OR2 s 2 1 0 1 ~755~8
- 6 - C 13 OR2 s 2 1 0 1 ~755~9
- 7 - C 13 OR2 s 0 4 0 1 ~755~10
- 8 - C 13 OR2 s 2 2 0 1 ~755~11
- 1 - C 13 AND2 0 4 0 3 :755
- 6 - C 01 OR2 s 0 2 0 3 ~786~1
- 7 - C 11 OR2 s 0 4 0 2 ~786~2
- 6 - C 11 DFFE + 0 4 1 0 :787
- 2 - C 09 OR2 0 2 0 4 :806
- 3 - C 11 DFFE + 0 4 1 0 :810
- 4 - C 09 DFFE + 0 4 1 0 :833
- 7 - C 09 AND2 ! 0 3 0 1 :852
- 1 - C 11 OR2 s 0 3 0 1 ~855~1
- 2 - C 15 OR2 s 0 4 0 3 ~855~2
- 2 - C 11 DFFE + 0 4 1 0 :856
- 8 - C 09 AND2 ! 0 4 0 2 :875
- 1 - C 09 DFFE + 0 4 1 0 :879
- 4 - C 11 AND2 ! 0 4 0 2 :898
- 8 - C 11 DFFE + 0 4 1 0 :902
- 5 - C 11 DFFE + 0 4 1 0 :925
- 1 - C 04 DFFE + 0 2 1 0 :936
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\论文\taxi1\sel3.rpt
sel3
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 1/ 48( 2%) 6/ 48( 12%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 87/ 96( 90%) 3/ 48( 6%) 21/ 48( 43%) 8/16( 50%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
24: 7/24( 29%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\论文\taxi1\sel3.rpt
sel3
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 24 clk1
Device-Specific Information: f:\论文\taxi1\sel3.rpt
sel3
** EQUATIONS **
clk1 : INPUT;
in10 : INPUT;
in11 : INPUT;
in12 : INPUT;
in13 : INPUT;
in20 : INPUT;
in21 : INPUT;
in22 : INPUT;
in23 : INPUT;
in30 : INPUT;
in31 : INPUT;
in32 : INPUT;
in33 : INPUT;
in40 : INPUT;
in41 : INPUT;
in42 : INPUT;
in43 : INPUT;
in50 : INPUT;
in51 : INPUT;
in52 : INPUT;
in53 : INPUT;
in60 : INPUT;
in61 : INPUT;
in62 : INPUT;
in63 : INPUT;
in70 : INPUT;
in71 : INPUT;
in72 : INPUT;
in73 : INPUT;
in80 : INPUT;
in81 : INPUT;
in82 : INPUT;
in83 : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = _LC6_C11;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = _LC3_C11;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = _LC4_C9;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = _LC2_C11;
-- Node name is 'e'
-- Equation name is 'e', type is output
e = _LC1_C9;
-- Node name is 'f'
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