📄 sel1.rpt
字号:
- 2 - I 38 OR2 s 3 1 0 1 ~708~1
- 2 - I 37 OR2 s 3 1 0 1 ~708~2
- 2 - I 33 OR2 s 3 1 0 1 ~708~3
- 5 - I 27 OR2 s 3 1 0 1 ~708~4
- 4 - I 43 OR2 s 3 1 0 1 ~708~5
- 2 - I 43 AND2 s 0 4 0 1 ~708~6
- 7 - I 47 OR2 s 0 4 0 1 ~708~7
- 4 - I 27 OR2 s 3 1 0 1 ~708~8
- 4 - I 38 OR2 s 1 2 0 1 ~708~9
- 6 - I 46 OR2 s 3 1 0 1 ~708~10
- 6 - I 38 AND2 s 0 4 0 1 ~708~11
- 7 - I 38 AND2 0 4 0 3 :708
- 1 - I 36 AND2 s 2 0 0 3 ~761~1
- 2 - I 46 OR2 s 0 2 0 1 ~761~2
- 8 - I 46 OR2 s 2 2 0 1 ~761~3
- 4 - I 37 OR2 s 2 2 0 1 ~761~4
- 1 - I 45 OR2 s 2 2 0 1 ~761~5
- 4 - I 45 OR2 s 2 2 0 1 ~761~6
- 1 - I 41 OR2 s 0 3 0 1 ~761~7
- 5 - I 45 OR2 s 2 2 0 1 ~761~8
- 6 - I 45 OR2 s 2 2 0 1 ~761~9
- 7 - I 45 OR2 s 2 2 0 1 ~761~10
- 2 - I 45 AND2 0 4 0 4 :761
- 3 - I 45 OR2 s 0 2 0 5 ~792~1
- 7 - I 30 OR2 s 0 2 0 4 ~792~2
- 2 - I 30 DFFE + 0 4 1 0 :793
- 5 - I 52 OR2 0 2 0 5 :812
- 4 - I 14 DFFE + 0 4 1 0 :816
- 1 - I 34 DFFE + 0 4 1 0 :839
- 4 - I 30 AND2 ! 0 3 0 1 :858
- 3 - I 38 OR2 s 0 3 0 3 ~861~1
- 1 - I 38 OR2 s 0 4 0 5 ~861~2
- 6 - I 30 DFFE + 0 4 1 0 :862
- 8 - I 30 AND2 ! 0 4 0 4 :881
- 6 - I 34 DFFE + 0 4 1 0 :885
- 5 - I 30 AND2 ! 0 4 0 4 :904
- 1 - I 14 DFFE + 0 4 1 0 :908
- 8 - I 38 DFFE + 0 4 1 0 :931
- 1 - I 30 DFFE + 0 4 1 0 :1031
- 2 - I 14 DFFE + 0 4 1 0 :1054
- 4 - I 34 DFFE + 0 4 1 0 :1077
- 3 - I 30 DFFE + 0 4 1 0 :1100
- 3 - I 34 DFFE + 0 4 1 0 :1123
- 3 - I 14 DFFE + 0 4 1 0 :1146
- 5 - I 38 DFFE + 0 4 1 0 :1169
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\论文\taxi1\sel1.rpt
sel1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 1/104( 0%) 1/104( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 1/104( 0%) 0/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
I: 97/208( 46%) 0/104( 0%) 27/104( 25%) 3/16( 18%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 1/104( 0%) 0/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
28: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
29: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
30: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
31: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
34: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
35: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
36: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
37: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
38: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
39: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
40: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
41: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
42: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
43: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
48: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
49: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
50: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
51: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
52: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\论文\taxi1\sel1.rpt
sel1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 30 clk1
Device-Specific Information: f:\论文\taxi1\sel1.rpt
sel1
** EQUATIONS **
clk1 : INPUT;
in10 : INPUT;
in11 : INPUT;
in12 : INPUT;
in13 : INPUT;
in20 : INPUT;
in21 : INPUT;
in22 : INPUT;
in23 : INPUT;
in30 : INPUT;
in31 : INPUT;
in32 : INPUT;
in33 : INPUT;
in40 : INPUT;
in41 : INPUT;
in42 : INPUT;
in43 : INPUT;
in50 : INPUT;
in51 : INPUT;
in52 : INPUT;
in53 : INPUT;
in60 : INPUT;
in61 : INPUT;
in62 : INPUT;
in63 : INPUT;
in70 : INPUT;
in71 : INPUT;
in72 : INPUT;
in73 : INPUT;
in80 : INPUT;
in81 : INPUT;
in82 : INPUT;
in83 : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = _LC2_I30;
-- Node name is 'a1'
-- Equation name is 'a1', type is output
a1 = _LC1_I30;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = _LC4_I14;
-- Node name is 'b1'
-- Equation name is 'b1', type is output
b1 = _LC2_I14;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = _LC1_I34;
-- Node name is 'c1'
-- Equation name is 'c1', type is output
c1 = _LC4_I34;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = _LC6_I30;
-- Node name is 'd1'
-- Equation name is 'd1', type is output
d1 = _LC3_I30;
-- Node name is 'e'
-- Equation name is 'e', type is output
e = _LC6_I34;
-- Node name is 'e1'
-- Equation name is 'e1', type is output
e1 = _LC3_I34;
-- Node name is 'f'
-- Equation name is 'f', type is output
f = _LC1_I14;
-- Node name is ':63' = 'flag10'
-- Equation name is 'flag10', location is LC4_I21, type is buried.
flag10 = DFFE(!flag10, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':62' = 'flag11'
-- Equation name is 'flag11', location is LC8_I21, type is buried.
flag11 = DFFE( _EQ001, GLOBAL( clk1), VCC, VCC, VCC);
_EQ001 = !flag10 & flag11
# flag10 & !flag11;
-- Node name is ':61' = 'flag12'
-- Equation name is 'flag12', location is LC2_I21, type is buried.
flag12 = DFFE( _EQ002, GLOBAL( clk1), VCC, VCC, VCC);
_EQ002 = !flag11 & flag12
# !flag10 & flag12
# flag10 & flag11 & !flag12;
-- Node name is ':60' = 'flag13'
-- Equation name is 'flag13', location is LC4_I2, type is buried.
flag13 = DFFE( _EQ003, GLOBAL( clk1), VCC, VCC, VCC);
_EQ003 = !flag11 & flag13
# !flag10 & flag13
# !flag12 & flag13
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