📄 sel1.rpt
字号:
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 8 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 5 8 0 0 0 0 0 7 2 8 8 8 7 5 4 8 3 8 8 8 1 8 1 6 4 8 6 8 8 1 7 0 8 175/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 8 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 5 8 0 0 0 0 0 7 2 8 8 8 7 5 4 8 3 8 8 8 1 8 1 6 4 8 6 8 8 1 7 0 8 175/0
Device-Specific Information: f:\论文\taxi1\sel1.rpt
sel1
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G ^ 0 0 0 0 clk1
187 - - - 28 INPUT ^ 0 0 0 6 in10
62 - - - 36 INPUT ^ 0 0 0 7 in11
78 - - - -- INPUT ^ 0 0 0 7 in12
205 - - - 50 INPUT ^ 0 0 0 8 in13
75 - - - 27 INPUT ^ 0 0 0 6 in20
203 - - - 48 INPUT ^ 0 0 0 7 in21
197 - - - 43 INPUT ^ 0 0 0 7 in22
58 - - - 42 INPUT ^ 0 0 0 8 in23
172 - - - 20 INPUT ^ 0 0 0 6 in30
70 - - - 31 INPUT ^ 0 0 0 7 in31
116 - - I -- INPUT ^ 0 0 0 7 in32
195 - - - 39 INPUT ^ 0 0 0 8 in33
38 - - I -- INPUT ^ 0 0 0 6 in40
89 - - - 18 INPUT ^ 0 0 0 6 in41
208 - - - 52 INPUT ^ 0 0 0 6 in42
184 - - - -- INPUT ^ 0 0 0 7 in43
37 - - I -- INPUT ^ 0 0 0 6 in50
57 - - - 43 INPUT ^ 0 0 0 5 in51
53 - - - 52 INPUT ^ 0 0 0 5 in52
182 - - - -- INPUT ^ 0 0 0 8 in53
95 - - - 09 INPUT ^ 0 0 0 6 in60
183 - - - -- INPUT ^ 0 0 0 7 in61
64 - - - 35 INPUT ^ 0 0 0 7 in62
196 - - - 41 INPUT ^ 0 0 0 8 in63
202 - - - 47 INPUT ^ 0 0 0 6 in70
60 - - - 40 INPUT ^ 0 0 0 7 in71
193 - - - 38 INPUT ^ 0 0 0 7 in72
63 - - - 35 INPUT ^ 0 0 0 8 in73
54 - - - 51 INPUT ^ 0 0 0 6 in80
204 - - - 49 INPUT ^ 0 0 0 7 in81
199 - - - 45 INPUT ^ 0 0 0 7 in82
80 - - - -- INPUT ^ 0 0 0 8 in83
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\论文\taxi1\sel1.rpt
sel1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
189 - - - 30 OUTPUT 0 1 0 0 a
73 - - - 29 OUTPUT 0 1 0 0 a1
94 - - - 13 OUTPUT 0 1 0 0 b
164 - - - 14 OUTPUT 0 1 0 0 b1
65 - - - 34 OUTPUT 0 1 0 0 c
67 - - - 33 OUTPUT 0 1 0 0 c1
15 - - C -- OUTPUT 0 1 0 0 d
71 - - - 30 OUTPUT 0 1 0 0 d1
68 - - - 33 OUTPUT 0 1 0 0 e
190 - - - 33 OUTPUT 0 1 0 0 e1
163 - - - 14 OUTPUT 0 1 0 0 f
93 - - - 14 OUTPUT 0 1 0 0 f1
25 - - E -- OUTPUT 0 1 0 0 g
192 - - - 37 OUTPUT 0 1 0 0 g1
113 - - K -- OUTPUT 0 1 0 0 ms1
103 - - - 02 OUTPUT 0 1 0 0 ms2
136 - - C -- OUTPUT 0 1 0 0 ms3
174 - - - 22 OUTPUT 0 1 0 0 ms4
175 - - - 22 OUTPUT 0 1 0 0 ms5
87 - - - 21 OUTPUT 0 1 0 0 ms6
173 - - - 21 OUTPUT 0 1 0 0 ms7
119 - - H -- OUTPUT 0 1 0 0 ms8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\论文\taxi1\sel1.rpt
sel1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - I 02 DFFE + 0 3 0 17 flag13 (:60)
- 2 - I 21 DFFE + 0 2 0 18 flag12 (:61)
- 8 - I 21 DFFE + 0 1 0 19 flag11 (:62)
- 4 - I 21 DFFE + 0 0 0 20 flag10 (:63)
- 7 - I 21 AND2 0 4 0 13 :68
- 5 - I 02 DFFE + 0 4 1 0 :86
- 2 - I 22 AND2 0 4 0 13 :91
- 8 - I 02 DFFE + 0 4 1 0 :101
- 5 - I 22 AND2 0 4 0 13 :106
- 7 - I 22 DFFE + 0 4 1 0 :116
- 3 - I 02 AND2 0 4 0 13 :121
- 6 - I 22 DFFE + 0 4 1 0 :131
- 7 - I 02 AND2 0 4 0 13 :136
- 1 - I 22 DFFE + 0 4 1 0 :146
- 1 - I 02 AND2 0 4 0 13 :151
- 3 - I 22 DFFE + 0 4 1 0 :161
- 2 - I 02 AND2 0 4 0 13 :166
- 4 - I 22 DFFE + 0 4 1 0 :176
- 6 - I 02 AND2 0 4 0 13 :181
- 8 - I 22 DFFE + 0 4 1 0 :191
- 3 - I 21 OR2 ! 0 4 0 13 :230
- 1 - I 31 OR2 s 2 2 0 1 ~268~1
- 4 - I 31 OR2 s 2 2 0 1 ~268~2
- 5 - I 31 OR2 s 1 2 0 1 ~268~3
- 6 - I 31 OR2 s 1 3 0 1 ~268~4
- 4 - I 29 OR2 s 2 2 0 1 ~268~5
- 3 - I 31 OR2 0 4 0 4 :268
- 1 - I 48 OR2 s 2 2 0 1 ~269~1
- 8 - I 45 OR2 s 2 2 0 1 ~269~2
- 5 - I 48 OR2 s 1 2 0 1 ~269~3
- 7 - I 48 OR2 s 1 3 0 1 ~269~4
- 3 - I 37 OR2 s 2 2 0 1 ~269~5
- 6 - I 48 OR2 0 4 0 5 :269
- 1 - I 39 OR2 s 2 2 0 1 ~270~1
- 2 - I 39 OR2 s 2 2 0 1 ~270~2
- 3 - I 39 OR2 s 1 2 0 1 ~270~3
- 4 - I 47 OR2 s 1 3 0 1 ~270~4
- 6 - I 52 OR2 s 2 2 0 1 ~270~5
- 6 - I 39 OR2 0 4 0 5 :270
- 2 - I 32 OR2 s 2 2 0 1 ~271~1
- 2 - I 29 OR2 s 2 2 0 1 ~271~2
- 3 - I 29 OR2 s 1 2 0 1 ~271~3
- 6 - I 29 OR2 s 1 3 0 1 ~271~4
- 3 - I 32 OR2 s 2 2 0 1 ~271~5
- 5 - I 29 OR2 0 4 0 6 :271
- 1 - I 44 DFFE + 0 1 0 8 temp3 (:272)
- 3 - I 48 DFFE + 0 1 0 7 temp2 (:273)
- 3 - I 44 DFFE + 0 1 0 7 temp1 (:274)
- 6 - I 44 DFFE + 0 1 0 6 temp0 (:275)
- 5 - I 47 AND2 s 0 4 0 1 ~284~1
- 8 - I 35 AND2 s 4 0 0 1 ~284~2
- 1 - I 43 AND2 s 4 0 0 1 ~284~3
- 1 - I 35 OR2 s 0 4 0 1 ~284~4
- 8 - I 36 OR2 s 2 2 0 1 ~284~5
- 6 - I 47 OR2 s 0 4 0 1 ~284~6
- 5 - I 33 AND2 s 4 0 0 1 ~284~7
- 1 - I 37 AND2 s 4 0 0 1 ~284~8
- 5 - I 37 OR2 s 0 4 0 1 ~284~9
- 3 - I 46 OR2 s 1 3 0 1 ~284~10
- 3 - I 27 AND2 s 4 0 0 1 ~284~11
- 7 - I 27 AND2 s 4 0 0 1 ~284~12
- 6 - I 27 OR2 s 0 4 0 1 ~284~13
- 2 - I 41 OR2 s 3 1 0 1 ~337~1
- 3 - I 41 OR2 s 3 0 0 1 ~337~2
- 6 - I 41 OR2 s 3 1 0 1 ~337~3
- 7 - I 41 OR2 s 0 4 0 1 ~337~4
- 8 - I 41 OR2 s 0 4 0 1 ~337~5
- 2 - I 27 OR2 s 3 0 0 1 ~337~6
- 8 - I 37 OR2 s 3 1 0 1 ~337~7
- 1 - I 42 AND2 s ! 3 0 0 2 ~337~8
- 8 - I 48 OR2 s 3 1 0 1 ~337~9
- 2 - I 48 OR2 s 0 4 0 1 ~337~10
- 4 - I 49 OR2 s 3 1 0 1 ~337~11
- 1 - I 27 OR2 s 0 4 0 1 ~337~12
- 4 - I 41 OR2 ! 0 4 0 6 :337
- 3 - I 43 OR2 s 3 1 0 1 ~390~1
- 4 - I 50 OR2 s 3 1 0 1 ~390~2
- 1 - I 46 OR2 s 3 1 0 1 ~390~3
- 7 - I 37 OR2 s 3 1 0 1 ~390~4
- 5 - I 28 OR2 s 3 1 0 1 ~390~5
- 7 - I 46 AND2 s 0 4 0 1 ~390~6
- 3 - I 35 OR2 s 0 4 0 1 ~390~7
- 6 - I 33 OR2 s 3 1 0 1 ~390~8
- 5 - I 35 OR2 s 3 1 0 1 ~390~9
- 6 - I 35 OR2 s 3 1 0 1 ~390~10
- 4 - I 35 AND2 s 0 4 0 1 ~390~11
- 8 - I 43 AND2 0 4 0 6 :390
- 7 - I 31 OR2 s 2 1 0 1 ~443~1
- 8 - I 31 OR2 s 2 2 0 1 ~443~2
- 2 - I 31 OR2 s 2 2 0 1 ~443~3
- 1 - I 50 OR2 s 2 2 0 1 ~443~4
- 3 - I 50 OR2 s 2 2 0 1 ~443~5
- 4 - I 48 OR2 s 0 3 0 1 ~443~6
- 5 - I 50 OR2 s 2 2 0 1 ~443~7
- 6 - I 50 OR2 s 2 2 0 1 ~443~8
- 7 - I 50 OR2 s 2 2 0 1 ~443~9
- 2 - I 50 AND2 0 4 0 3 :443
- 3 - I 40 OR2 s 3 1 0 1 ~496~1
- 6 - I 37 OR2 s 3 1 0 1 ~496~2
- 1 - I 33 OR2 s 3 1 0 1 ~496~3
- 4 - I 28 OR2 s 3 1 0 1 ~496~4
- 7 - I 43 OR2 s 3 1 0 1 ~496~5
- 4 - I 33 AND2 s ! 0 4 0 1 ~496~6
- 2 - I 47 OR2 s 0 4 0 1 ~496~7
- 5 - I 41 OR2 s 3 1 0 1 ~496~8
- 4 - I 36 OR2 s 3 1 0 1 ~496~9
- 5 - I 39 OR2 s 3 1 0 1 ~496~10
- 3 - I 47 AND2 s ! 0 4 0 1 ~496~11
- 1 - I 47 AND2 0 4 0 11 :496
- 7 - I 39 OR2 s 2 1 0 1 ~549~1
- 8 - I 39 OR2 s 2 2 0 1 ~549~2
- 4 - I 39 OR2 s 2 2 0 1 ~549~3
- 1 - I 52 OR2 s 2 2 0 1 ~549~4
- 2 - I 52 OR2 s 2 2 0 1 ~549~5
- 8 - I 47 OR2 s 0 3 0 1 ~549~6
- 4 - I 52 OR2 s 2 2 0 1 ~549~7
- 7 - I 52 OR2 s 2 2 0 1 ~549~8
- 8 - I 52 OR2 s 2 2 0 1 ~549~9
- 3 - I 52 AND2 0 4 0 2 :549
- 7 - I 29 OR2 s 2 1 0 1 ~602~1
- 8 - I 29 OR2 s 2 2 0 1 ~602~2
- 1 - I 29 OR2 s 2 2 0 1 ~602~3
- 1 - I 32 OR2 s 2 2 0 1 ~602~4
- 4 - I 32 OR2 s 2 2 0 1 ~602~5
- 7 - I 35 OR2 s 0 3 0 1 ~602~6
- 2 - I 35 OR2 s 2 2 0 1 ~602~7
- 5 - I 32 OR2 s 2 2 0 1 ~602~8
- 6 - I 32 OR2 s 2 2 0 1 ~602~9
- 8 - I 32 AND2 0 4 0 5 :602
- 2 - I 44 OR2 ! 0 4 0 6 :655
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