sel2.rpt

出租车计价器

10:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
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EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                            f:\论文\taxi1\sel2.rpt
sel2

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        8         clk


Device-Specific Information:                            f:\论文\taxi1\sel2.rpt
sel2

** EQUATIONS **

clk      : INPUT;
in10     : INPUT;
in11     : INPUT;
in12     : INPUT;
in13     : INPUT;
in20     : INPUT;
in21     : INPUT;
in22     : INPUT;
in23     : INPUT;
in30     : INPUT;
in31     : INPUT;
in32     : INPUT;
in33     : INPUT;
in40     : INPUT;
in41     : INPUT;
in42     : INPUT;
in43     : INPUT;

-- Node name is ':33' = 'cnt0' 
-- Equation name is 'cnt0', location is LC8_B7, type is buried.
cnt0     = DFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 = !cnt0 & !cnt1 & !cnt2 & !cnt3
         #  cnt0 &  cnt1
         #  cnt0 &  cnt3
         #  cnt0 &  cnt2;

-- Node name is ':32' = 'cnt1' 
-- Equation name is 'cnt1', location is LC1_B9, type is buried.
cnt1     = DFFE( _LC6_B7, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':31' = 'cnt2' 
-- Equation name is 'cnt2', location is LC6_B9, type is buried.
cnt2     = DFFE( _LC2_B7, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':30' = 'cnt3' 
-- Equation name is 'cnt3', location is LC4_B7, type is buried.
cnt3     = DFFE( _LC3_B7, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is 'daout0' 
-- Equation name is 'daout0', type is output 
daout0   =  _LC1_B1;

-- Node name is 'daout1' 
-- Equation name is 'daout1', type is output 
daout1   =  _LC2_B2;

-- Node name is 'daout2' 
-- Equation name is 'daout2', type is output 
daout2   =  _LC5_B2;

-- Node name is 'daout3' 
-- Equation name is 'daout3', type is output 
daout3   =  _LC8_B9;

-- Node name is 'sel20' 
-- Equation name is 'sel20', type is output 
sel20    =  cnt3;

-- Node name is 'sel21' 
-- Equation name is 'sel21', type is output 
sel21    =  cnt2;

-- Node name is 'sel22' 
-- Equation name is 'sel22', type is output 
sel22    =  cnt1;

-- Node name is 'sel23' 
-- Equation name is 'sel23', type is output 
sel23    =  cnt0;

-- Node name is ':22' 
-- Equation name is '_LC8_B9', type is buried 
_LC8_B9  = DFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 = !_LC2_B9 &  _LC7_B9
         #  in13 &  _LC2_B9;

-- Node name is ':24' 
-- Equation name is '_LC5_B2', type is buried 
_LC5_B2  = DFFE( _EQ003, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 = !_LC2_B9 &  _LC7_B2
         #  in12 &  _LC2_B9;

-- Node name is ':26' 
-- Equation name is '_LC2_B2', type is buried 
_LC2_B2  = DFFE( _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 = !_LC2_B9 &  _LC4_B2
         #  in11 &  _LC2_B9;

-- Node name is ':28' 
-- Equation name is '_LC1_B1', type is buried 
_LC1_B1  = DFFE( _EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 = !_LC2_B9 &  _LC8_B2
         #  in10 &  _LC2_B9;

-- Node name is ':67' 
-- Equation name is '_LC1_B7', type is buried 
_LC1_B7  = LCELL( _EQ006);
  _EQ006 =  cnt0 & !cnt1 & !cnt2 & !cnt3;

-- Node name is ':111' 
-- Equation name is '_LC3_B7', type is buried 
_LC3_B7  = LCELL( _EQ007);
  _EQ007 =  cnt3
         # !cnt0 & !cnt1 &  cnt2;

-- Node name is ':126' 
-- Equation name is '_LC2_B7', type is buried 
_LC2_B7  = LCELL( _EQ008);
  _EQ008 = !cnt0 &  cnt1 & !cnt3
         #  cnt2 &  cnt3
         #  cnt0 &  cnt2
         #  cnt1 &  cnt2;

-- Node name is ':141' 
-- Equation name is '_LC6_B7', type is buried 
_LC6_B7  = LCELL( _EQ009);
  _EQ009 =  cnt0 & !cnt2 & !cnt3
         #  cnt1 &  cnt2
         #  cnt1 &  cnt3
         #  cnt0 &  cnt1;

-- Node name is ':154' 
-- Equation name is '_LC5_B7', type is buried 
_LC5_B7  = LCELL( _EQ010);
  _EQ010 = !cnt0 & !cnt1 & !cnt2 & !cnt3
         #  cnt0 &  cnt3
         #  cnt0 &  cnt2
         #  cnt0 &  cnt1;

-- Node name is ':238' 
-- Equation name is '_LC3_B9', type is buried 
_LC3_B9  = LCELL( _EQ011);
  _EQ011 = !cnt0 & !_LC2_B7 &  _LC3_B7 & !_LC6_B7;

-- Node name is ':250' 
-- Equation name is '_LC5_B9', type is buried 
_LC5_B9  = LCELL( _EQ012);
  _EQ012 = !cnt0 &  _LC2_B7 & !_LC3_B7 & !_LC6_B7;

-- Node name is ':253' 
-- Equation name is '_LC4_B9', type is buried 
_LC4_B9  = LCELL( _EQ013);
  _EQ013 =  in33 &  _LC5_B9
         #  in43 &  _LC3_B9;

-- Node name is '~262~1' 
-- Equation name is '~262~1', location is LC7_B7, type is buried.
-- synthesized logic cell 
_LC7_B7  = LCELL( _EQ014);
  _EQ014 =  _LC1_B7 & !_LC2_B7 & !_LC3_B7
         # !cnt0 & !_LC2_B7 & !_LC3_B7;

-- Node name is ':265' 
-- Equation name is '_LC7_B9', type is buried 
_LC7_B9  = LCELL( _EQ015);
  _EQ015 =  _LC4_B9 & !_LC7_B7
         #  _LC4_B9 & !_LC6_B7
         #  in23 &  _LC6_B7 &  _LC7_B7;

-- Node name is ':274' 
-- Equation name is '_LC2_B9', type is buried 
_LC2_B9  = LCELL( _EQ016);
  _EQ016 = !_LC2_B7 & !_LC3_B7 &  _LC5_B7 & !_LC6_B7;

-- Node name is ':286' 
-- Equation name is '_LC6_B2', type is buried 
_LC6_B2  = LCELL( _EQ017);
  _EQ017 =  in32 &  _LC5_B9
         #  in42 &  _LC3_B9;

-- Node name is ':289' 
-- Equation name is '_LC7_B2', type is buried 
_LC7_B2  = LCELL( _EQ018);
  _EQ018 =  _LC6_B2 & !_LC7_B7
         #  _LC6_B2 & !_LC6_B7
         #  in22 &  _LC6_B7 &  _LC7_B7;

-- Node name is ':301' 
-- Equation name is '_LC3_B2', type is buried 
_LC3_B2  = LCELL( _EQ019);
  _EQ019 =  in31 &  _LC5_B9
         #  in41 &  _LC3_B9;

-- Node name is ':304' 
-- Equation name is '_LC4_B2', type is buried 
_LC4_B2  = LCELL( _EQ020);
  _EQ020 =  _LC3_B2 & !_LC7_B7
         #  _LC3_B2 & !_LC6_B7
         #  in21 &  _LC6_B7 &  _LC7_B7;

-- Node name is ':316' 
-- Equation name is '_LC1_B2', type is buried 
_LC1_B2  = LCELL( _EQ021);
  _EQ021 =  in30 &  _LC5_B9
         #  in40 &  _LC3_B9;

-- Node name is ':319' 
-- Equation name is '_LC8_B2', type is buried 
_LC8_B2  = LCELL( _EQ022);
  _EQ022 =  _LC1_B2 & !_LC7_B7
         #  _LC1_B2 & !_LC6_B7
         #  in20 &  _LC6_B7 &  _LC7_B7;



Project Information                                     f:\论文\taxi1\sel2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 37,582K