📄 sel2.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sel2 is
port (clk:in std_logic;
in1,in2,in3,in4:in std_logic_vector(3 downto 0);
sel2:out std_logic_vector(0 downto 3);
daout:out std_logic_vector(3 downto 0));
end sel2;
architecture sel_arc of sel2 is
begin
PROCESS (clk)
VARIABLE cnt:std_logic_vector(3 downto 0);
BEGIN
IF(clk'event AND CLK='1')THEN
if cnt="0000"then
cnt:="0001";
elsif cnt="0001"then
cnt:="0010";
elsif cnt="0010"then
cnt:="0100";
elsif cnt="0100"then
cnt:="1000";
end if;
case cnt is
when"0001"=>daout<=in1;
when"0010"=>daout<=in2;
when"0100"=>daout<=in3;
when"1000"=>daout<=in4;
when others=>daout<="0000";
end case;
end if;
sel2<=cnt;
end process;
end sel_arc;
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