fdivision.rpt

出租车计价器

-- Node name is ':92' = 'j14' 
-- Equation name is 'j14', location is LC3_A19, type is buried.
j14      = DFFE( _EQ014, GLOBAL( F40M),  VCC,  VCC,  VCC);
  _EQ014 = !j13 &  j14 & !_LC1_A6
         #  j14 & !_LC1_A2 & !_LC1_A6
         #  j13 & !j14 &  _LC1_A2 & !_LC1_A6;

-- Node name is ':91' = 'j15' 
-- Equation name is 'j15', location is LC2_A5, type is buried.
j15      = DFFE( _EQ015, GLOBAL( F40M),  VCC,  VCC,  VCC);
  _EQ015 = !j14 &  j15 & !_LC1_A6
         #  j15 & !_LC1_A6 & !_LC7_A5
         #  j14 & !j15 & !_LC1_A6 &  _LC7_A5;

-- Node name is ':90' = 'j16' 
-- Equation name is 'j16', location is LC8_A19, type is buried.
j16      = DFFE( _EQ016, GLOBAL( F40M),  VCC,  VCC,  VCC);
  _EQ016 =  j16 & !_LC1_A6 & !_LC4_A19
         # !j16 & !_LC1_A6 &  _LC4_A19;

-- Node name is ':89' = 'j17' 
-- Equation name is 'j17', location is LC7_A19, type is buried.
j17      = DFFE( _EQ017, GLOBAL( F40M),  VCC,  VCC,  VCC);
  _EQ017 = !j16 &  j17 & !_LC1_A6
         #  j17 & !_LC1_A6 & !_LC4_A19
         #  j16 & !j17 & !_LC1_A6 &  _LC4_A19;

-- Node name is ':88' = 'j18' 
-- Equation name is 'j18', location is LC6_A19, type is buried.
j18      = DFFE( _EQ018, GLOBAL( F40M),  VCC,  VCC,  VCC);
  _EQ018 =  j18 & !_LC1_A6 & !_LC5_A19
         # !j18 & !_LC1_A6 &  _LC5_A19;

-- Node name is ':87' = 'j19' 
-- Equation name is 'j19', location is LC3_A3, type is buried.
j19      = DFFE( _EQ019, GLOBAL( F40M),  VCC,  VCC,  VCC);
  _EQ019 =  j19 & !_LC1_A6 & !_LC2_A19
         # !j19 & !_LC1_A6 &  _LC2_A19;

-- Node name is ':86' = 'j20' 
-- Equation name is 'j20', location is LC8_A1, type is buried.
j20      = DFFE( _EQ020, GLOBAL( F40M),  VCC,  VCC,  VCC);
  _EQ020 = !j19 &  j20 & !_LC1_A6
         #  j20 & !_LC1_A6 & !_LC2_A19
         #  j19 & !j20 & !_LC1_A6 &  _LC2_A19;

-- Node name is ':85' = 'j21' 
-- Equation name is 'j21', location is LC7_A1, type is buried.
j21      = DFFE( _EQ021, GLOBAL( F40M),  VCC,  VCC,  VCC);
  _EQ021 =  j21 & !_LC1_A6 & !_LC3_A1
         # !j21 & !_LC1_A6 &  _LC3_A1;

-- Node name is ':84' = 'j22' 
-- Equation name is 'j22', location is LC6_A1, type is buried.
j22      = DFFE( _EQ022, GLOBAL( F40M),  VCC,  VCC,  VCC);
  _EQ022 = !j21 &  j22 & !_LC1_A6
         #  j22 & !_LC1_A6 & !_LC3_A1
         #  j21 & !j22 & !_LC1_A6 &  _LC3_A1;

-- Node name is ':83' = 'j23' 
-- Equation name is 'j23', location is LC5_A1, type is buried.
j23      = DFFE( _EQ023, GLOBAL( F40M),  VCC,  VCC,  VCC);
  _EQ023 = !j22 &  j23 & !_LC1_A6
         #  j23 & !_LC1_A6 & !_LC4_A1
         #  j22 & !j23 & !_LC1_A6 &  _LC4_A1;

-- Node name is '|lpm_add_sub:110|addcore:adder|:135' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A5', type is buried 
_LC1_A5  = LCELL( _EQ024);
  _EQ024 =  j0 &  j1;

-- Node name is '|lpm_add_sub:110|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A6', type is buried 
_LC3_A6  = LCELL( _EQ025);
  _EQ025 =  j2 &  j3 &  _LC1_A5;

-- Node name is '|lpm_add_sub:110|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A6', type is buried 
_LC4_A6  = LCELL( _EQ026);
  _EQ026 =  j4 &  _LC3_A6;

-- Node name is '|lpm_add_sub:110|addcore:adder|:155' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A6', type is buried 
_LC2_A6  = LCELL( _EQ027);
  _EQ027 =  j5 &  j6 &  _LC4_A6;

-- Node name is '|lpm_add_sub:110|addcore:adder|:159' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A3', type is buried 
_LC5_A3  = LCELL( _EQ028);
  _EQ028 =  j7 &  _LC2_A6;

-- Node name is '|lpm_add_sub:110|addcore:adder|:167' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A2', type is buried 
_LC4_A2  = LCELL( _EQ029);
  _EQ029 =  j7 &  j8 &  j9 &  _LC2_A6;

-- Node name is '|lpm_add_sub:110|addcore:adder|:171' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A2', type is buried 
_LC5_A2  = LCELL( _EQ030);
  _EQ030 =  j10 &  _LC4_A2;

-- Node name is '|lpm_add_sub:110|addcore:adder|:179' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A2', type is buried 
_LC1_A2  = LCELL( _EQ031);
  _EQ031 =  j11 &  j12 &  _LC5_A2;

-- Node name is '|lpm_add_sub:110|addcore:adder|:183' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A5', type is buried 
_LC7_A5  = LCELL( _EQ032);
  _EQ032 =  j13 &  _LC1_A2;

-- Node name is '|lpm_add_sub:110|addcore:adder|:191' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A19', type is buried 
_LC4_A19 = LCELL( _EQ033);
  _EQ033 =  j13 &  j14 &  j15 &  _LC1_A2;

-- Node name is '|lpm_add_sub:110|addcore:adder|:199' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A19', type is buried 
_LC5_A19 = LCELL( _EQ034);
  _EQ034 =  j16 &  j17 &  _LC4_A19;

-- Node name is '|lpm_add_sub:110|addcore:adder|:203' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A19', type is buried 
_LC2_A19 = LCELL( _EQ035);
  _EQ035 =  j16 &  j17 &  j18 &  _LC4_A19;

-- Node name is '|lpm_add_sub:110|addcore:adder|:211' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = LCELL( _EQ036);
  _EQ036 =  j19 &  j20 &  _LC2_A19;

-- Node name is '|lpm_add_sub:110|addcore:adder|:215' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A1', type is buried 
_LC4_A1  = LCELL( _EQ037);
  _EQ037 =  j21 &  _LC3_A1;

-- Node name is '~4~1' 
-- Equation name is '~4~1', location is LC2_A2, type is buried.
-- synthesized logic cell 
!_LC2_A2 = _LC2_A2~NOT;
_LC2_A2~NOT = LCELL( _EQ038);
  _EQ038 = !j12 & !j13 &  j14 & !j15;

-- Node name is '~4~2' 
-- Equation name is '~4~2', location is LC1_A19, type is buried.
-- synthesized logic cell 
!_LC1_A19 = _LC1_A19~NOT;
_LC1_A19~NOT = LCELL( _EQ039);
  _EQ039 = !j16 & !j17 & !j18 & !j19;

-- Node name is '~4~3' 
-- Equation name is '~4~3', location is LC2_A1, type is buried.
-- synthesized logic cell 
!_LC2_A1 = _LC2_A1~NOT;
_LC2_A1~NOT = LCELL( _EQ040);
  _EQ040 = !j21 & !j22 & !j23;

-- Node name is '~4~4' 
-- Equation name is '~4~4', location is LC1_A1, type is buried.
-- synthesized logic cell 
!_LC1_A1 = _LC1_A1~NOT;
_LC1_A1~NOT = LCELL( _EQ041);
  _EQ041 = !j20 & !_LC1_A19 & !_LC2_A1 & !_LC2_A2;

-- Node name is '~4~5' 
-- Equation name is '~4~5', location is LC5_A6, type is buried.
-- synthesized logic cell 
!_LC5_A6 = _LC5_A6~NOT;
_LC5_A6~NOT = LCELL( _EQ042);
  _EQ042 = !j5 & !j6 & !j7;

-- Node name is '~4~6' 
-- Equation name is '~4~6', location is LC3_A2, type is buried.
-- synthesized logic cell 
!_LC3_A2 = _LC3_A2~NOT;
_LC3_A2~NOT = LCELL( _EQ043);
  _EQ043 = !j8 &  j9 &  j10 &  j11;

-- Node name is ':4' 
-- Equation name is '_LC1_A6', type is buried 
_LC1_A6  = LCELL( _EQ044);
  _EQ044 = !_LC1_A1 & !_LC3_A2 &  _LC4_A6 & !_LC5_A6;

-- Node name is ':108' 
-- Equation name is '_LC4_A3', type is buried 
_LC4_A3  = DFFE(!_LC4_A3, GLOBAL( F40M),  VCC,  VCC,  _LC1_A6);



Project Information                                f:\论文\taxi1\fdivision.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:07


Memory Allocated
-----------------

Peak memory allocated during compilation  = 118,318K