📄 fdivision.rpt
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fdivision
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
149 - - A -- OUTPUT 0 1 0 0 F1K
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\论文\taxi1\fdivision.rpt
fdivision
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 05 AND2 0 2 0 3 |lpm_add_sub:110|addcore:adder|:135
- 3 - A 06 AND2 0 3 0 3 |lpm_add_sub:110|addcore:adder|:143
- 4 - A 06 AND2 0 2 0 3 |lpm_add_sub:110|addcore:adder|:147
- 2 - A 06 AND2 0 3 0 4 |lpm_add_sub:110|addcore:adder|:155
- 5 - A 03 AND2 0 2 0 1 |lpm_add_sub:110|addcore:adder|:159
- 4 - A 02 AND2 0 4 0 2 |lpm_add_sub:110|addcore:adder|:167
- 5 - A 02 AND2 0 2 0 3 |lpm_add_sub:110|addcore:adder|:171
- 1 - A 02 AND2 0 3 0 4 |lpm_add_sub:110|addcore:adder|:179
- 7 - A 05 AND2 0 2 0 1 |lpm_add_sub:110|addcore:adder|:183
- 4 - A 19 AND2 0 4 0 4 |lpm_add_sub:110|addcore:adder|:191
- 5 - A 19 AND2 0 3 0 1 |lpm_add_sub:110|addcore:adder|:199
- 2 - A 19 AND2 0 4 0 3 |lpm_add_sub:110|addcore:adder|:203
- 3 - A 01 AND2 0 3 0 3 |lpm_add_sub:110|addcore:adder|:211
- 4 - A 01 AND2 0 2 0 1 |lpm_add_sub:110|addcore:adder|:215
- 2 - A 02 AND2 s ! 0 4 0 1 ~4~1
- 1 - A 19 AND2 s ! 0 4 0 1 ~4~2
- 2 - A 01 AND2 s ! 0 3 0 1 ~4~3
- 1 - A 01 AND2 s ! 0 4 0 1 ~4~4
- 5 - A 06 AND2 s ! 0 3 0 1 ~4~5
- 3 - A 02 AND2 s ! 0 4 0 1 ~4~6
- 1 - A 06 AND2 0 4 0 24 :4
- 5 - A 01 DFFE + 0 3 0 1 j23 (:83)
- 6 - A 01 DFFE + 0 3 0 2 j22 (:84)
- 7 - A 01 DFFE + 0 2 0 3 j21 (:85)
- 8 - A 01 DFFE + 0 3 0 2 j20 (:86)
- 3 - A 03 DFFE + 0 2 0 3 j19 (:87)
- 6 - A 19 DFFE + 0 2 0 2 j18 (:88)
- 7 - A 19 DFFE + 0 3 0 3 j17 (:89)
- 8 - A 19 DFFE + 0 2 0 4 j16 (:90)
- 2 - A 05 DFFE + 0 3 0 2 j15 (:91)
- 3 - A 19 DFFE + 0 3 0 3 j14 (:92)
- 5 - A 05 DFFE + 0 2 0 4 j13 (:93)
- 6 - A 02 DFFE + 0 3 0 2 j12 (:94)
- 7 - A 02 DFFE + 0 2 0 3 j11 (:95)
- 8 - A 02 DFFE + 0 2 0 2 j10 (:96)
- 6 - A 03 DFFE + 0 3 0 2 j9 (:97)
- 2 - A 03 DFFE + 0 3 0 3 j8 (:98)
- 1 - A 03 DFFE + 0 2 0 4 j7 (:99)
- 7 - A 06 DFFE + 0 3 0 2 j6 (:100)
- 8 - A 06 DFFE + 0 3 0 3 j5 (:101)
- 6 - A 06 DFFE + 0 2 0 2 j4 (:102)
- 8 - A 05 DFFE + 0 3 0 1 j3 (:103)
- 4 - A 05 DFFE + 0 2 0 2 j2 (:104)
- 3 - A 05 DFFE + 0 2 0 1 j1 (:105)
- 6 - A 05 DFFE + 0 0 0 2 j0 (:106)
- 4 - A 03 DFFE + 0 1 1 0 :108
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\论文\taxi1\fdivision.rpt
fdivision
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 18/208( 8%) 1/104( 0%) 0/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
51: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\论文\taxi1\fdivision.rpt
fdivision
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 25 F40M
Device-Specific Information: f:\论文\taxi1\fdivision.rpt
fdivision
** EQUATIONS **
F40M : INPUT;
-- Node name is 'F1K'
-- Equation name is 'F1K', type is output
F1K = _LC4_A3;
-- Node name is ':106' = 'j0'
-- Equation name is 'j0', location is LC6_A5, type is buried.
j0 = DFFE(!j0, GLOBAL( F40M), VCC, VCC, VCC);
-- Node name is ':105' = 'j1'
-- Equation name is 'j1', location is LC3_A5, type is buried.
j1 = DFFE( _EQ001, GLOBAL( F40M), VCC, VCC, VCC);
_EQ001 = j0 & !j1 & !_LC1_A6
# !j0 & j1 & !_LC1_A6;
-- Node name is ':104' = 'j2'
-- Equation name is 'j2', location is LC4_A5, type is buried.
j2 = DFFE( _EQ002, GLOBAL( F40M), VCC, VCC, VCC);
_EQ002 = j2 & !_LC1_A5 & !_LC1_A6
# !j2 & _LC1_A5 & !_LC1_A6;
-- Node name is ':103' = 'j3'
-- Equation name is 'j3', location is LC8_A5, type is buried.
j3 = DFFE( _EQ003, GLOBAL( F40M), VCC, VCC, VCC);
_EQ003 = !j2 & j3 & !_LC1_A6
# j3 & !_LC1_A5 & !_LC1_A6
# j2 & !j3 & _LC1_A5 & !_LC1_A6;
-- Node name is ':102' = 'j4'
-- Equation name is 'j4', location is LC6_A6, type is buried.
j4 = DFFE( _EQ004, GLOBAL( F40M), VCC, VCC, VCC);
_EQ004 = j4 & !_LC1_A6 & !_LC3_A6
# !j4 & !_LC1_A6 & _LC3_A6;
-- Node name is ':101' = 'j5'
-- Equation name is 'j5', location is LC8_A6, type is buried.
j5 = DFFE( _EQ005, GLOBAL( F40M), VCC, VCC, VCC);
_EQ005 = !j4 & j5 & !_LC1_A6
# j5 & !_LC1_A6 & !_LC3_A6
# j4 & !j5 & !_LC1_A6 & _LC3_A6;
-- Node name is ':100' = 'j6'
-- Equation name is 'j6', location is LC7_A6, type is buried.
j6 = DFFE( _EQ006, GLOBAL( F40M), VCC, VCC, VCC);
_EQ006 = !j5 & j6 & !_LC1_A6
# j6 & !_LC1_A6 & !_LC4_A6
# j5 & !j6 & !_LC1_A6 & _LC4_A6;
-- Node name is ':99' = 'j7'
-- Equation name is 'j7', location is LC1_A3, type is buried.
j7 = DFFE( _EQ007, GLOBAL( F40M), VCC, VCC, VCC);
_EQ007 = j7 & !_LC1_A6 & !_LC2_A6
# !j7 & !_LC1_A6 & _LC2_A6;
-- Node name is ':98' = 'j8'
-- Equation name is 'j8', location is LC2_A3, type is buried.
j8 = DFFE( _EQ008, GLOBAL( F40M), VCC, VCC, VCC);
_EQ008 = !j7 & j8 & !_LC1_A6
# j8 & !_LC1_A6 & !_LC2_A6
# j7 & !j8 & !_LC1_A6 & _LC2_A6;
-- Node name is ':97' = 'j9'
-- Equation name is 'j9', location is LC6_A3, type is buried.
j9 = DFFE( _EQ009, GLOBAL( F40M), VCC, VCC, VCC);
_EQ009 = !j8 & j9 & !_LC1_A6
# j9 & !_LC1_A6 & !_LC5_A3
# j8 & !j9 & !_LC1_A6 & _LC5_A3;
-- Node name is ':96' = 'j10'
-- Equation name is 'j10', location is LC8_A2, type is buried.
j10 = DFFE( _EQ010, GLOBAL( F40M), VCC, VCC, VCC);
_EQ010 = j10 & !_LC1_A6 & !_LC4_A2
# !j10 & !_LC1_A6 & _LC4_A2;
-- Node name is ':95' = 'j11'
-- Equation name is 'j11', location is LC7_A2, type is buried.
j11 = DFFE( _EQ011, GLOBAL( F40M), VCC, VCC, VCC);
_EQ011 = j11 & !_LC1_A6 & !_LC5_A2
# !j11 & !_LC1_A6 & _LC5_A2;
-- Node name is ':94' = 'j12'
-- Equation name is 'j12', location is LC6_A2, type is buried.
j12 = DFFE( _EQ012, GLOBAL( F40M), VCC, VCC, VCC);
_EQ012 = !j11 & j12 & !_LC1_A6
# j12 & !_LC1_A6 & !_LC5_A2
# j11 & !j12 & !_LC1_A6 & _LC5_A2;
-- Node name is ':93' = 'j13'
-- Equation name is 'j13', location is LC5_A5, type is buried.
j13 = DFFE( _EQ013, GLOBAL( F40M), VCC, VCC, VCC);
_EQ013 = j13 & !_LC1_A2 & !_LC1_A6
# !j13 & _LC1_A2 & !_LC1_A6;
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