📄 taxi.rpt
字号:
94 - - - 13 INPUT ^ 0 0 0 1 flag
95 - - - 09 INPUT ^ 0 0 0 51 reset
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\论文\taxi1\taxi.rpt
taxi
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
195 - - - 39 OUTPUT 0 1 0 0 a
175 - - - 22 OUTPUT 0 1 0 0 a1
196 - - - 41 OUTPUT 0 1 0 0 b
176 - - - 23 OUTPUT 0 1 0 0 b1
197 - - - 43 OUTPUT 0 1 0 0 c
177 - - - 24 OUTPUT 0 1 0 0 c1
198 - - - 44 OUTPUT 0 1 0 0 d
179 - - - 25 OUTPUT 0 1 0 0 d1
199 - - - 45 OUTPUT 0 1 0 0 e
180 - - - 26 OUTPUT 0 1 0 0 e1
200 - - - 46 OUTPUT 0 1 0 0 f
186 - - - 27 OUTPUT 0 1 0 0 f1
202 - - - 47 OUTPUT 0 1 0 0 g
187 - - - 28 OUTPUT 0 1 0 0 g1
116 - - I -- OUTPUT 0 1 0 0 ifw
190 - - - 33 OUTPUT 0 1 0 0 ms1
191 - - - 35 OUTPUT 0 1 0 0 ms2
192 - - - 37 OUTPUT 0 1 0 0 ms3
193 - - - 38 OUTPUT 0 1 0 0 ms4
170 - - - 19 OUTPUT 0 1 0 0 ms5
172 - - - 20 OUTPUT 0 1 0 0 ms6
173 - - - 21 OUTPUT 0 1 0 0 ms7
174 - - - 22 OUTPUT 0 1 0 0 ms8
203 - - - 48 OUTPUT 0 1 0 0 p
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\论文\taxi1\taxi.rpt
taxi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 25 OR2 ! 0 2 0 3 |FEN:135|LPM_ADD_SUB:195|addcore:adder|:127
- 2 - C 40 OR2 ! 0 3 0 2 |FEN:135|LPM_ADD_SUB:195|addcore:adder|:135
- 3 - C 40 OR2 ! 0 2 0 3 |FEN:135|LPM_ADD_SUB:195|addcore:adder|:139
- 2 - C 39 AND2 0 3 0 4 |FEN:135|LPM_ADD_SUB:195|addcore:adder|:155
- 3 - C 39 AND2 0 3 0 1 |FEN:135|LPM_ADD_SUB:195|addcore:adder|:163
- 3 - C 42 AND2 0 4 0 4 |FEN:135|LPM_ADD_SUB:195|addcore:adder|:167
- 6 - C 42 AND2 0 2 0 1 |FEN:135|LPM_ADD_SUB:195|addcore:adder|:171
- 2 - C 42 AND2 0 4 0 4 |FEN:135|LPM_ADD_SUB:195|addcore:adder|:179
- 8 - C 25 AND2 0 2 0 1 |FEN:135|LPM_ADD_SUB:195|addcore:adder|:183
- 4 - C 24 AND2 0 4 0 3 |FEN:135|LPM_ADD_SUB:195|addcore:adder|:191
- 7 - C 24 AND2 0 2 0 1 |FEN:135|LPM_ADD_SUB:195|addcore:adder|:195
- 3 - H 39 OR2 ! 0 2 0 3 |FEN:135|LPM_ADD_SUB:534|addcore:adder|:103
- 1 - H 39 OR2 ! 0 3 0 3 |FEN:135|LPM_ADD_SUB:534|addcore:adder|:111
- 5 - H 51 AND2 0 4 0 4 |FEN:135|LPM_ADD_SUB:534|addcore:adder|:123
- 3 - H 51 AND2 0 3 0 1 |FEN:135|LPM_ADD_SUB:534|addcore:adder|:131
- 1 - H 51 AND2 0 4 0 4 |FEN:135|LPM_ADD_SUB:534|addcore:adder|:135
- 6 - H 28 AND2 0 3 0 1 |FEN:135|LPM_ADD_SUB:534|addcore:adder|:143
- 4 - H 28 AND2 0 4 0 2 |FEN:135|LPM_ADD_SUB:534|addcore:adder|:147
- 6 - C 25 DFFE + 0 1 0 65 |FEN:135|b (|FEN:135|:4)
- 6 - H 37 DFFE + 0 1 0 39 |FEN:135|a (|FEN:135|:5)
- 8 - C 24 DFFE + 0 3 0 1 |FEN:135|cnt20 (|FEN:135|:6)
- 6 - C 24 DFFE + 0 3 0 2 |FEN:135|cnt19 (|FEN:135|:7)
- 5 - C 24 DFFE + 0 2 0 3 |FEN:135|cnt18 (|FEN:135|:8)
- 3 - C 24 DFFE + 0 3 0 2 |FEN:135|cnt17 (|FEN:135|:9)
- 3 - C 25 DFFE + 0 3 0 3 |FEN:135|cnt16 (|FEN:135|:10)
- 4 - C 25 DFFE + 0 2 0 4 |FEN:135|cnt15 (|FEN:135|:11)
- 7 - C 42 DFFE + 0 3 0 2 |FEN:135|cnt14 (|FEN:135|:12)
- 5 - C 42 DFFE + 0 3 0 3 |FEN:135|cnt13 (|FEN:135|:13)
- 4 - C 42 DFFE + 0 2 0 4 |FEN:135|cnt12 (|FEN:135|:14)
- 1 - C 42 DFFE + 0 2 0 2 |FEN:135|cnt11 (|FEN:135|:15)
- 4 - C 39 DFFE + 0 3 0 3 |FEN:135|cnt10 (|FEN:135|:16)
- 5 - C 39 DFFE + 0 2 0 4 |FEN:135|cnt9 (|FEN:135|:17)
- 8 - C 39 DFFE + 0 3 0 2 |FEN:135|cnt8 (|FEN:135|:18)
- 7 - C 39 DFFE + 0 2 0 3 |FEN:135|cnt7 (|FEN:135|:19)
- 7 - C 40 DFFE + 0 3 0 1 |FEN:135|cnt6 (|FEN:135|:20)
- 8 - C 40 DFFE + 0 2 0 2 |FEN:135|cnt5 (|FEN:135|:21)
- 6 - C 40 DFFE + 0 2 0 1 |FEN:135|cnt4 (|FEN:135|:22)
- 4 - C 40 DFFE + 0 3 0 1 |FEN:135|cnt3 (|FEN:135|:23)
- 5 - C 40 DFFE + 0 2 0 2 |FEN:135|cnt2 (|FEN:135|:24)
- 7 - C 25 DFFE + 0 2 0 1 |FEN:135|cnt1 (|FEN:135|:25)
- 5 - C 25 DFFE + 0 1 0 2 |FEN:135|cnt0 (|FEN:135|:26)
- 1 - C 24 OR2 s 0 4 0 1 |FEN:135|~50~1
- 2 - C 24 OR2 0 4 0 22 |FEN:135|:50
- 8 - C 42 AND2 s 0 4 0 1 |FEN:135|~77~1
- 1 - C 39 OR2 0 4 0 1 |FEN:135|:77
- 6 - C 39 AND2 s 0 3 0 1 |FEN:135|~102~1
- 1 - C 40 OR2 0 3 0 4 |FEN:135|:120
- 5 - H 28 DFFE + 0 3 0 1 |FEN:135|cnt114 (|FEN:135|:399)
- 8 - H 28 DFFE + 0 2 0 2 |FEN:135|cnt113 (|FEN:135|:400)
- 7 - H 28 DFFE + 0 2 0 2 |FEN:135|cnt112 (|FEN:135|:401)
- 2 - H 28 DFFE + 0 3 0 3 |FEN:135|cnt111 (|FEN:135|:402)
- 3 - H 28 DFFE + 0 2 0 4 |FEN:135|cnt110 (|FEN:135|:403)
- 3 - H 37 DFFE + 0 2 0 2 |FEN:135|cnt19~147 (|FEN:135|:404)
- 4 - H 51 DFFE + 0 3 0 3 |FEN:135|cnt18~147 (|FEN:135|:405)
- 8 - H 51 DFFE + 0 2 0 4 |FEN:135|cnt17~147 (|FEN:135|:406)
- 7 - H 51 DFFE + 0 3 0 2 |FEN:135|cnt16~147 (|FEN:135|:407)
- 6 - H 51 DFFE + 0 2 0 3 |FEN:135|cnt15~147 (|FEN:135|:408)
- 8 - H 39 DFFE + 0 2 0 2 |FEN:135|cnt14~147 (|FEN:135|:409)
- 6 - H 39 DFFE + 0 3 0 1 |FEN:135|cnt13~147 (|FEN:135|:410)
- 7 - H 39 DFFE + 0 2 0 2 |FEN:135|cnt12~147 (|FEN:135|:411)
- 5 - H 39 DFFE + 0 2 0 1 |FEN:135|cnt11~147 (|FEN:135|:412)
- 4 - H 39 DFFE + 0 1 0 2 |FEN:135|cnt10~147 (|FEN:135|:413)
- 1 - H 28 OR2 0 4 0 16 |FEN:135|:431
- 2 - H 37 OR2 s 0 3 0 1 |FEN:135|~446~1
- 1 - H 37 OR2 0 4 0 1 |FEN:135|:446
- 2 - H 51 AND2 s 0 3 0 1 |FEN:135|~458~1
- 2 - H 39 OR2 0 2 0 3 |FEN:135|:481
- 4 - H 32 AND2 0 2 0 4 |ntaxi:39|lpm_add_sub:1169|addcore:adder|:67
- 5 - H 32 AND2 0 2 0 1 |ntaxi:39|lpm_add_sub:1169|addcore:adder|:71
- 2 - H 32 AND2 0 3 0 3 |ntaxi:39|lpm_add_sub:1169|addcore:adder|:75
- 6 - H 42 AND2 0 2 0 1 |ntaxi:39|lpm_add_sub:1169|addcore:adder|:79
- 1 - F 12 AND2 0 2 0 3 |ntaxi:39|lpm_add_sub:1170|addcore:adder|:55
- 7 - F 30 AND2 0 2 0 1 |ntaxi:39|lpm_add_sub:1171|addcore:adder|:55
- 1 - F 30 AND2 0 3 0 1 |ntaxi:39|lpm_add_sub:1171|addcore:adder|:59
- 8 - E 25 OR2 ! 0 2 0 4 |ntaxi:39|lpm_add_sub:1172|addcore:adder|:63
- 2 - E 01 AND2 0 3 0 2 |ntaxi:39|lpm_add_sub:1172|addcore:adder|:71
- 5 - B 27 AND2 0 2 0 2 |ntaxi:39|lpm_add_sub:1174|addcore:adder|:55
- 1 - B 13 AND2 0 2 0 1 |ntaxi:39|lpm_add_sub:1175|addcore:adder|:55
- 1 - B 17 AND2 0 3 0 1 |ntaxi:39|lpm_add_sub:1175|addcore:adder|:59
- 4 - B 26 AND2 0 2 0 1 |ntaxi:39|lpm_add_sub:1176|addcore:adder|:55
- 1 - B 11 OR2 ! 0 2 0 1 |ntaxi:39|lpm_add_sub:1177|addcore:adder|:55
- 7 - C 15 AND2 0 2 0 2 |ntaxi:39|lpm_add_sub:1178|addcore:adder|:55
- 5 - F 01 AND2 0 2 0 1 |ntaxi:39|lpm_add_sub:1179|addcore:adder|:55
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