📄 taxi.rpt
字号:
E E E E E E N E E E E E E C E E E E E C E E E N C N N N N N E C E E E E E E C E E l e E E C E E E E E E
S S S S S S D S S S S S S C S S S S S C S S S D C D D D D D S C S S S S S S C S S a s S S C S S S S S S
E E E E E E E E E E E E I E E E E E I E E E I E I E E E E E E I E E g e E E I E E E E E E
R R R R R R R R R R R R O R R R R R N R R R N R O R R R R R R N R R t R R O R R R R R R
V V V V V V V V V V V V V V V V V T V V V T V V V V V V V T V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: f:\论文\taxi1\taxi.rpt
taxi
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B5 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 7/26( 26%)
B6 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/26( 23%)
B9 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 11/26( 42%)
B11 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/26( 23%)
B13 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/26( 26%)
B17 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 7/26( 26%)
B21 8/ 8(100%) 6/ 8( 75%) 0/ 8( 0%) 2/2 0/2 10/26( 38%)
B26 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 9/26( 34%)
B27 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/26( 23%)
B28 4/ 8( 50%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 4/26( 15%)
B31 4/ 8( 50%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 11/26( 42%)
B32 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 2/2 0/2 13/26( 50%)
B33 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 3/26( 11%)
B35 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/26( 7%)
B36 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 11/26( 42%)
B37 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 13/26( 50%)
B38 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 18/26( 69%)
B40 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 15/26( 57%)
B42 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 20/26( 76%)
B43 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 8/26( 30%)
B44 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 13/26( 50%)
B45 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 20/26( 76%)
B46 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 5/26( 19%)
B47 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 20/26( 76%)
B48 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 10/26( 38%)
B49 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 15/26( 57%)
B51 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 19/26( 73%)
C15 8/ 8(100%) 5/ 8( 62%) 3/ 8( 37%) 2/2 0/2 8/26( 30%)
C16 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 6/26( 23%)
C24 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 5/26( 19%)
C25 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 2/2 0/2 5/26( 19%)
C39 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 3/26( 11%)
C40 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/26( 7%)
C42 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 5/26( 19%)
E1 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 6/26( 23%)
E25 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 5/26( 19%)
F1 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 9/26( 34%)
F3 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 15/26( 57%)
F4 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 10/26( 38%)
F6 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 15/26( 57%)
F7 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 10/26( 38%)
F9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 3/26( 11%)
F10 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 15/26( 57%)
F11 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 1/2 0/2 3/26( 11%)
F12 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 17/26( 65%)
F14 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 8/26( 30%)
F19 5/ 8( 62%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 2/26( 7%)
F20 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 15/26( 57%)
F21 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 13/26( 50%)
F22 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 15/26( 57%)
F24 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 18/26( 69%)
F25 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 14/26( 53%)
F28 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 19/26( 73%)
F30 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/26( 23%)
F39 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 9/26( 34%)
H28 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 2/26( 7%)
H32 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 6/26( 23%)
H37 5/ 8( 62%) 3/ 8( 37%) 2/ 8( 25%) 2/2 0/2 8/26( 30%)
H39 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 1/26( 3%)
H42 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 6/26( 23%)
H51 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/26( 19%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 26/141 ( 18%)
Total logic cells used: 442/4992 ( 8%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
Average fan-in: 3.48/4 ( 87%)
Total fan-in: 1542/19968 ( 7%)
Total input pins required: 3
Total input I/O cell registers required: 0
Total output pins required: 24
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 442
Total flipflops required: 143
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 171/4992 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 8 3 0 0 8 0 8 0 6 0 0 0 7 0 0 0 8 0 0 0 0 7 0 8 4 0 0 4 8 8 0 1 8 8 8 0 8 0 8 8 8 8 1 7 7 8 0 8 0 183/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 0 0 0 0 0 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 8 0 0 0 0 0 0 0 0 0 0 56/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16/0
F: 8 0 8 8 0 8 8 0 1 8 8 8 0 8 0 0 0 0 5 8 8 8 0 8 8 0 0 0 8 0 8 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 142/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 8 0 0 0 0 5 0 8 0 0 8 0 0 0 0 0 0 0 0 8 0 45/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 16 0 8 8 8 11 8 0 9 8 16 8 6 8 8 8 7 0 5 8 16 8 0 16 24 7 0 8 20 0 8 4 16 8 0 1 8 13 8 24 16 0 24 8 8 8 1 7 7 8 0 16 0 442/0
Device-Specific Information: f:\论文\taxi1\taxi.rpt
taxi
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
183 - - - -- INPUT G ^ 0 0 0 0 CLK
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