📄 sel.rpt
字号:
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 5 8 0 0 0 0 0 0 3 0 8 8 8 1 4 1 8 8 3 8 0 8 8 8 8 0 8 8 8 8 8 8 8 0 169/0
Device-Specific Information: f:\论文\taxi1\sel.rpt
sel
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G ^ 0 0 0 0 clk1
207 - - - 51 INPUT ^ 0 0 0 6 in10
62 - - - 36 INPUT ^ 0 0 0 7 in11
191 - - - 35 INPUT ^ 0 0 0 7 in12
58 - - - 42 INPUT ^ 0 0 0 8 in13
197 - - - 43 INPUT ^ 0 0 0 6 in20
200 - - - 46 INPUT ^ 0 0 0 6 in21
193 - - - 38 INPUT ^ 0 0 0 6 in22
202 - - - 47 INPUT ^ 0 0 0 7 in23
135 - - D -- INPUT ^ 0 0 0 6 in30
195 - - - 39 INPUT ^ 0 0 0 7 in31
199 - - - 45 INPUT ^ 0 0 0 7 in32
57 - - - 43 INPUT ^ 0 0 0 8 in33
75 - - - 27 INPUT ^ 0 0 0 6 in40
67 - - - 33 INPUT ^ 0 0 0 7 in41
190 - - - 33 INPUT ^ 0 0 0 7 in42
192 - - - 37 INPUT ^ 0 0 0 8 in43
65 - - - 34 INPUT ^ 0 0 0 6 in50
196 - - - 41 INPUT ^ 0 0 0 5 in51
186 - - - 27 INPUT ^ 0 0 0 5 in52
182 - - - -- INPUT ^ 0 0 0 8 in53
56 - - - 45 INPUT ^ 0 0 0 6 in60
60 - - - 40 INPUT ^ 0 0 0 7 in61
183 - - - -- INPUT ^ 0 0 0 7 in62
73 - - - 29 INPUT ^ 0 0 0 8 in63
64 - - - 35 INPUT ^ 0 0 0 6 in70
134 - - D -- INPUT ^ 0 0 0 7 in71
184 - - - -- INPUT ^ 0 0 0 7 in72
80 - - - -- INPUT ^ 0 0 0 8 in73
187 - - - 28 INPUT ^ 0 0 0 6 in80
53 - - - 52 INPUT ^ 0 0 0 7 in81
78 - - - -- INPUT ^ 0 0 0 7 in82
133 - - D -- INPUT ^ 0 0 0 8 in83
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\论文\taxi1\sel.rpt
sel
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
206 - - - 50 OUTPUT 0 1 0 0 a
17 - - D -- OUTPUT 0 1 0 0 b
15 - - C -- OUTPUT 0 1 0 0 c
16 - - D -- OUTPUT 0 1 0 0 d
71 - - - 30 OUTPUT 0 1 0 0 e
204 - - - 49 OUTPUT 0 1 0 0 f
19 - - D -- OUTPUT 0 1 0 0 g
88 - - - 19 OUTPUT 0 1 0 0 ms1
174 - - - 22 OUTPUT 0 1 0 0 ms2
170 - - - 19 OUTPUT 0 1 0 0 ms3
169 - - - 18 OUTPUT 0 1 0 0 ms4
87 - - - 21 OUTPUT 0 1 0 0 ms5
175 - - - 22 OUTPUT 0 1 0 0 ms6
168 - - - 17 OUTPUT 0 1 0 0 ms7
89 - - - 18 OUTPUT 0 1 0 0 ms8
18 - - D -- OUTPUT 0 1 0 0 p
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\论文\taxi1\sel.rpt
sel
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - D 17 DFFE + 0 3 0 17 flag13 (:54)
- 5 - D 20 DFFE + 0 2 0 18 flag12 (:55)
- 7 - D 20 DFFE + 0 1 0 19 flag11 (:56)
- 6 - D 20 DFFE + 0 0 0 20 flag10 (:57)
- 6 - D 17 AND2 0 4 0 13 :62
- 2 - D 20 DFFE + 0 4 1 0 :80
- 6 - D 21 AND2 0 4 0 14 :85
- 5 - D 21 DFFE + 0 4 1 0 :95
- 4 - D 21 AND2 0 4 0 13 :100
- 1 - D 20 DFFE + 0 4 1 0 :110
- 4 - D 17 AND2 0 4 0 13 :115
- 5 - D 17 DFFE + 0 4 1 0 :125
- 3 - D 21 AND2 0 4 0 13 :130
- 1 - D 21 DFFE + 0 4 1 0 :140
- 7 - D 21 AND2 0 4 0 13 :145
- 2 - D 21 DFFE + 0 4 1 0 :155
- 3 - D 17 AND2 0 4 0 13 :160
- 2 - D 17 DFFE + 0 4 1 0 :170
- 7 - D 17 AND2 0 4 0 13 :175
- 8 - D 17 DFFE + 0 4 1 0 :185
- 8 - D 21 OR2 ! 0 4 0 13 :224
- 1 - D 36 OR2 s 2 2 0 1 ~262~1
- 4 - D 38 OR2 s 2 2 0 1 ~262~2
- 1 - D 33 OR2 s 1 2 0 1 ~262~3
- 2 - D 36 OR2 s 1 3 0 1 ~262~4
- 5 - D 36 OR2 s 2 2 0 1 ~262~5
- 3 - D 36 OR2 0 4 0 4 :262
- 1 - D 51 OR2 s 2 2 0 1 ~263~1
- 2 - D 51 OR2 s 2 2 0 1 ~263~2
- 3 - D 51 OR2 s 1 2 0 1 ~263~3
- 5 - D 51 OR2 s 1 3 0 1 ~263~4
- 5 - D 47 OR2 s 2 2 0 1 ~263~5
- 4 - D 51 OR2 0 4 0 5 :263
- 1 - D 48 OR2 s 2 2 0 1 ~264~1
- 4 - D 48 OR2 s 2 2 0 1 ~264~2
- 7 - D 48 OR2 s 1 2 0 1 ~264~3
- 8 - D 48 OR2 s 1 3 0 1 ~264~4
- 3 - D 31 OR2 s 2 2 0 1 ~264~5
- 2 - D 48 OR2 0 4 0 5 :264
- 2 - D 38 OR2 s 2 2 0 1 ~265~1
- 2 - D 33 OR2 s 2 2 0 1 ~265~2
- 7 - D 33 OR2 s 1 2 0 1 ~265~3
- 4 - D 43 OR2 s 1 3 0 1 ~265~4
- 5 - D 43 OR2 s 2 2 0 1 ~265~5
- 3 - D 43 OR2 0 4 0 6 :265
- 6 - D 48 DFFE + 0 1 0 8 temp3 (:266)
- 1 - D 32 DFFE + 0 1 0 7 temp2 (:267)
- 3 - D 48 DFFE + 0 1 0 7 temp1 (:268)
- 2 - D 34 DFFE + 0 1 0 6 temp0 (:269)
- 4 - D 40 AND2 s 0 4 0 1 ~278~1
- 6 - D 49 AND2 s 4 0 0 1 ~278~2
- 7 - D 49 AND2 s 4 0 0 1 ~278~3
- 3 - D 49 OR2 s 0 4 0 1 ~278~4
- 3 - D 37 OR2 s 2 2 0 1 ~278~5
- 2 - D 30 OR2 s 0 4 0 1 ~278~6
- 6 - D 46 AND2 s 4 0 0 1 ~278~7
- 8 - D 42 AND2 s 4 0 0 1 ~278~8
- 6 - D 42 OR2 s 0 4 0 1 ~278~9
- 4 - D 30 OR2 s 1 3 0 1 ~278~10
- 5 - D 30 AND2 s 4 0 0 1 ~278~11
- 6 - D 27 AND2 s 4 0 0 1 ~278~12
- 8 - D 30 OR2 s 0 4 0 1 ~278~13
- 6 - D 37 OR2 s 3 1 0 1 ~331~1
- 1 - D 49 OR2 s 3 0 0 1 ~331~2
- 2 - D 49 OR2 s 3 1 0 1 ~331~3
- 4 - D 49 OR2 s 0 4 0 1 ~331~4
- 8 - D 49 OR2 s 0 4 0 1 ~331~5
- 1 - D 29 OR2 s 3 1 0 1 ~331~6
- 3 - D 29 OR2 s 3 0 0 1 ~331~7
- 1 - D 43 OR2 s 3 1 0 1 ~331~8
- 7 - D 42 OR2 s 3 1 0 1 ~331~9
- 7 - D 29 OR2 s 0 4 0 1 ~331~10
- 6 - D 29 AND2 s ! 3 0 0 2 ~331~11
- 2 - D 29 OR2 s 0 4 0 1 ~331~12
- 1 - D 45 OR2 ! 0 4 0 4 :331
- 3 - D 47 OR2 s 3 1 0 1 ~384~1
- 1 - D 42 OR2 s 3 1 0 1 ~384~2
- 4 - D 35 OR2 s 3 1 0 1 ~384~3
- 5 - D 35 OR2 s 3 1 0 1 ~384~4
- 6 - D 35 OR2 s 3 1 0 1 ~384~5
- 7 - D 35 AND2 s 0 4 0 1 ~384~6
- 5 - D 40 OR2 s 0 4 0 1 ~384~7
- 3 - D 41 OR2 s 3 1 0 1 ~384~8
- 5 - D 38 OR2 s 3 1 0 1 ~384~9
- 7 - D 40 OR2 s 3 1 0 1 ~384~10
- 6 - D 40 AND2 s 0 4 0 1 ~384~11
- 8 - D 35 AND2 0 4 0 5 :384
- 6 - D 51 OR2 s 2 1 0 1 ~437~1
- 7 - D 51 OR2 s 2 2 0 1 ~437~2
- 8 - D 51 OR2 s 2 2 0 1 ~437~3
- 1 - D 47 OR2 s 2 2 0 1 ~437~4
- 2 - D 47 OR2 s 2 2 0 1 ~437~5
- 2 - D 40 OR2 s 0 3 0 1 ~437~6
- 6 - D 47 OR2 s 2 2 0 1 ~437~7
- 7 - D 47 OR2 s 2 2 0 1 ~437~8
- 8 - D 47 OR2 s 2 2 0 1 ~437~9
- 4 - D 47 AND2 0 4 0 4 :437
- 8 - D 29 OR2 s 3 1 0 1 ~490~1
- 6 - D 43 OR2 s 3 1 0 1 ~490~2
- 1 - D 30 OR2 s 3 1 0 1 ~490~3
- 7 - D 43 OR2 s 3 1 0 1 ~490~4
- 8 - D 43 OR2 s 3 1 0 1 ~490~5
- 2 - D 43 AND2 s ! 0 4 0 1 ~490~6
- 3 - D 40 OR2 s 0 4 0 1 ~490~7
- 4 - D 41 OR2 s 3 1 0 1 ~490~8
- 5 - D 41 OR2 s 3 1 0 1 ~490~9
- 6 - D 41 OR2 s 3 1 0 1 ~490~10
- 7 - D 41 AND2 s ! 0 4 0 1 ~490~11
- 8 - D 41 AND2 0 4 0 6 :490
- 6 - D 36 OR2 s 2 1 0 1 ~543~1
- 7 - D 36 OR2 s 2 2 0 1 ~543~2
- 8 - D 36 OR2 s 2 2 0 1 ~543~3
- 4 - D 36 OR2 s 2 2 0 1 ~543~4
- 4 - D 29 OR2 s 2 2 0 1 ~543~5
- 1 - D 41 OR2 s 0 3 0 1 ~543~6
- 2 - D 41 OR2 s 2 2 0 1 ~543~7
- 3 - D 45 OR2 s 2 2 0 1 ~543~8
- 4 - D 45 OR2 s 2 2 0 1 ~543~9
- 5 - D 45 AND2 0 4 0 2 :543
- 1 - D 35 OR2 s 2 1 0 1 ~596~1
- 3 - D 35 OR2 s 2 2 0 1 ~596~2
- 2 - D 35 OR2 s 2 2 0 1 ~596~3
- 1 - D 38 OR2 s 2 2 0 1 ~596~4
- 3 - D 38 OR2 s 2 2 0 1 ~596~5
- 1 - D 40 OR2 s 0 3 0 1 ~596~6
- 4 - D 27 OR2 s 2 2 0 1 ~596~7
- 6 - D 38 OR2 s 2 2 0 1 ~596~8
- 7 - D 38 OR2 s 2 2 0 1 ~596~9
- 8 - D 38 AND2 0 4 0 3 :596
- 5 - D 48 OR2 ! 0 4 0 4 :649
- 5 - D 29 OR2 s 3 1 0 1 ~702~1
- 4 - D 46 OR2 s 3 1 0 1 ~702~2
- 5 - D 46 OR2 s 3 1 0 1 ~702~3
- 5 - D 49 OR2 s 3 1 0 1 ~702~4
- 7 - D 46 OR2 s 3 1 0 1 ~702~5
- 8 - D 46 AND2 s 0 4 0 1 ~702~6
- 8 - D 40 OR2 s 0 4 0 1 ~702~7
- 8 - D 27 OR2 s 3 1 0 1 ~702~8
- 2 - D 42 OR2 s 1 2 0 1 ~702~9
- 3 - D 42 OR2 s 3 1 0 1 ~702~10
- 5 - D 42 AND2 s 0 4 0 1 ~702~11
- 1 - D 46 AND2 0 4 0 2 :702
- 4 - D 42 OR2 s 2 1 0 1 ~755~1
- 3 - D 46 OR2 s 2 2 0 1 ~755~2
- 2 - D 46 OR2 s 2 2 0 1 ~755~3
- 1 - D 31 OR2 s 2 2 0 1 ~755~4
- 2 - D 31 OR2 s 2 2 0 1 ~755~5
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