fdivision1.v

来自「出租车计价器」· Verilog 代码 · 共 53 行

module fdivision1(F40M,F1H,F1K); 

input F40M; 

output F1H,F1K; 

reg F1H,F1K;

reg[23:0]j,i; 

always @(posedge F40M) 

begin 

if(j==19999999) //对计数器进行判断，以确定F1H信号是否反转。 

begin 

j <= 0; 

F1H<= ~F1H; 

end 

else 

j <= j+1; 

end 
always @(posedge F40M)   

begin

if(i==19999)  

begin 

i<= 0; 

F1K <= ~F1K; 

end 

else 

i <= i+1; 

end 


endmodule