fen.vhd

出租车计价器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fen is
port(clk:in std_logic;
     clk1,clk1k:out std_logic
    );
end fen;
architecture fre of fen is
signal a,b:std_logic;
begin
process(clk)
variable cnt:integer range 0 to 1999999;
begin
 if clk'event and clk='1'then
   if cnt<1999999 then
      cnt:=cnt+1;
   else cnt:=0;
        b<=not b;
   end if;
end if;
clk1<=b;
end process;
process(clk)
variable cnt1:integer range 0 to 19999;
begin
if clk'event and clk='1'then
   if cnt1<19999 then
      cnt1:=cnt1+1;
   else cnt1:=0;
        a<=not a;
   end if;
end if;
clk1k<=a;
end process;
end fre;