📄 fen.rpt
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-- Node name is '|LPM_ADD_SUB:195|addcore:adder|:139' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C19', type is buried
!_LC3_C19 = _LC3_C19~NOT;
_LC3_C19~NOT = LCELL( _EQ041);
_EQ041 = !cnt4
# !_LC1_C19;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|:155' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C12', type is buried
_LC2_C12 = LCELL( _EQ042);
_EQ042 = cnt7 & cnt8 & !_LC2_C19;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|:163' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C12', type is buried
_LC5_C12 = LCELL( _EQ043);
_EQ043 = cnt9 & cnt10 & _LC2_C12;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|:167' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C13', type is buried
_LC3_C13 = LCELL( _EQ044);
_EQ044 = cnt9 & cnt10 & cnt11 & _LC2_C12;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|:171' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C13', type is buried
_LC6_C13 = LCELL( _EQ045);
_EQ045 = cnt12 & _LC3_C13;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|:179' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C13', type is buried
_LC2_C13 = LCELL( _EQ046);
_EQ046 = cnt12 & cnt13 & cnt14 & _LC3_C13;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|:183' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C16', type is buried
_LC3_C16 = LCELL( _EQ047);
_EQ047 = cnt15 & _LC2_C13;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|:191' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C6', type is buried
_LC4_C6 = LCELL( _EQ048);
_EQ048 = cnt15 & cnt16 & cnt17 & _LC2_C13;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|:195' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C6', type is buried
_LC7_C6 = LCELL( _EQ049);
_EQ049 = cnt18 & _LC4_C6;
-- Node name is '|LPM_ADD_SUB:534|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_G19', type is buried
!_LC2_G19 = _LC2_G19~NOT;
_LC2_G19~NOT = LCELL( _EQ050);
_EQ050 = !cnt10~147
# !cnt11~147;
-- Node name is '|LPM_ADD_SUB:534|addcore:adder|:111' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_G19', type is buried
!_LC4_G19 = _LC4_G19~NOT;
_LC4_G19~NOT = LCELL( _EQ051);
_EQ051 = !cnt13~147
# !cnt12~147
# !_LC2_G19;
-- Node name is '|LPM_ADD_SUB:534|addcore:adder|:123' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_G8', type is buried
_LC4_G8 = LCELL( _EQ052);
_EQ052 = cnt14~147 & cnt15~147 & cnt16~147 & _LC4_G19;
-- Node name is '|LPM_ADD_SUB:534|addcore:adder|:131' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_G8', type is buried
_LC3_G8 = LCELL( _EQ053);
_EQ053 = cnt17~147 & cnt18~147 & _LC4_G8;
-- Node name is '|LPM_ADD_SUB:534|addcore:adder|:135' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_G8', type is buried
_LC1_G8 = LCELL( _EQ054);
_EQ054 = cnt17~147 & cnt18~147 & cnt19~147 & _LC4_G8;
-- Node name is '|LPM_ADD_SUB:534|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_G1', type is buried
_LC4_G1 = LCELL( _EQ055);
_EQ055 = cnt110 & cnt111 & _LC1_G8;
-- Node name is '|LPM_ADD_SUB:534|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_G1', type is buried
_LC1_G1 = LCELL( _EQ056);
_EQ056 = cnt110 & cnt111 & cnt112 & _LC1_G8;
-- Node name is '~50~1'
-- Equation name is '~50~1', location is LC2_C6, type is buried.
-- synthesized logic cell
_LC2_C6 = LCELL( _EQ057);
_EQ057 = !cnt17
# !cnt18
# !cnt19
# !cnt20;
-- Node name is ':50'
-- Equation name is '_LC1_C6', type is buried
_LC1_C6 = LCELL( _EQ058);
_EQ058 = !cnt15 & !cnt16
# !cnt16 & _LC8_C13
# _LC2_C6;
-- Node name is '~77~1'
-- Equation name is '~77~1', location is LC1_C13, type is buried.
-- synthesized logic cell
_LC1_C13 = LCELL( _EQ059);
_EQ059 = !cnt11 & !cnt12 & !cnt13 & !cnt14;
-- Node name is ':77'
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = LCELL( _EQ060);
_EQ060 = !cnt10 & _LC1_C13
# _LC1_C13 & _LC2_C19 & _LC8_C12;
-- Node name is '~102~1'
-- Equation name is '~102~1', location is LC8_C12, type is buried.
-- synthesized logic cell
_LC8_C12 = LCELL( _EQ061);
_EQ061 = !cnt7 & !cnt8 & !cnt9;
-- Node name is ':120'
-- Equation name is '_LC2_C19', type is buried
_LC2_C19 = LCELL( _EQ062);
_EQ062 = !cnt6
# !cnt5
# !_LC3_C19;
-- Node name is ':431'
-- Equation name is '_LC2_G1', type is buried
_LC2_G1 = LCELL( _EQ063);
_EQ063 = !cnt114
# !cnt112 & !cnt113 & _LC2_G8;
-- Node name is '~446~1'
-- Equation name is '~446~1', location is LC2_G17, type is buried.
-- synthesized logic cell
_LC2_G17 = LCELL( _EQ064);
_EQ064 = !cnt19~147
# !cnt110
# !cnt111;
-- Node name is ':446'
-- Equation name is '_LC2_G8', type is buried
_LC2_G8 = LCELL( _EQ065);
_EQ065 = !cnt18~147 & _LC5_G8 & _LC6_G19
# _LC2_G17;
-- Node name is '~458~1'
-- Equation name is '~458~1', location is LC5_G8, type is buried.
-- synthesized logic cell
_LC5_G8 = LCELL( _EQ066);
_EQ066 = !cnt15~147 & !cnt16~147 & !cnt17~147;
-- Node name is ':481'
-- Equation name is '_LC6_G19', type is buried
_LC6_G19 = LCELL( _EQ067);
_EQ067 = !cnt14~147
# !_LC4_G19;
Project Information f:\论文\taxi1\fen.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:04
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 66,131K
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