📄 fen.rpt
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Total: 8 0 0 0 0 8 0 8 0 0 0 8 8 0 0 7 4 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67/0
Device-Specific Information: f:\论文\taxi1\fen.rpt
fen
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G ^ 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\论文\taxi1\fen.rpt
fen
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
136 - - C -- OUTPUT 0 1 0 0 clk1
122 - - G -- OUTPUT 0 1 0 0 clk1k
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\论文\taxi1\fen.rpt
fen
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 16 OR2 ! 0 2 0 3 |LPM_ADD_SUB:195|addcore:adder|:127
- 1 - C 19 OR2 ! 0 3 0 2 |LPM_ADD_SUB:195|addcore:adder|:135
- 3 - C 19 OR2 ! 0 2 0 3 |LPM_ADD_SUB:195|addcore:adder|:139
- 2 - C 12 AND2 0 3 0 4 |LPM_ADD_SUB:195|addcore:adder|:155
- 5 - C 12 AND2 0 3 0 1 |LPM_ADD_SUB:195|addcore:adder|:163
- 3 - C 13 AND2 0 4 0 4 |LPM_ADD_SUB:195|addcore:adder|:167
- 6 - C 13 AND2 0 2 0 1 |LPM_ADD_SUB:195|addcore:adder|:171
- 2 - C 13 AND2 0 4 0 4 |LPM_ADD_SUB:195|addcore:adder|:179
- 3 - C 16 AND2 0 2 0 1 |LPM_ADD_SUB:195|addcore:adder|:183
- 4 - C 06 AND2 0 4 0 3 |LPM_ADD_SUB:195|addcore:adder|:191
- 7 - C 06 AND2 0 2 0 1 |LPM_ADD_SUB:195|addcore:adder|:195
- 2 - G 19 OR2 ! 0 2 0 3 |LPM_ADD_SUB:534|addcore:adder|:103
- 4 - G 19 OR2 ! 0 3 0 3 |LPM_ADD_SUB:534|addcore:adder|:111
- 4 - G 08 AND2 0 4 0 4 |LPM_ADD_SUB:534|addcore:adder|:123
- 3 - G 08 AND2 0 3 0 1 |LPM_ADD_SUB:534|addcore:adder|:131
- 1 - G 08 AND2 0 4 0 4 |LPM_ADD_SUB:534|addcore:adder|:135
- 4 - G 01 AND2 0 3 0 1 |LPM_ADD_SUB:534|addcore:adder|:143
- 1 - G 01 AND2 0 4 0 2 |LPM_ADD_SUB:534|addcore:adder|:147
- 8 - C 16 DFFE + 0 1 1 0 b (:4)
- 1 - G 17 DFFE + 0 1 1 0 a (:5)
- 8 - C 06 DFFE + 0 3 0 1 cnt20 (:6)
- 6 - C 06 DFFE + 0 3 0 2 cnt19 (:7)
- 5 - C 06 DFFE + 0 2 0 3 cnt18 (:8)
- 3 - C 06 DFFE + 0 3 0 2 cnt17 (:9)
- 2 - C 16 DFFE + 0 3 0 3 cnt16 (:10)
- 4 - C 16 DFFE + 0 2 0 4 cnt15 (:11)
- 7 - C 13 DFFE + 0 3 0 2 cnt14 (:12)
- 5 - C 13 DFFE + 0 3 0 3 cnt13 (:13)
- 4 - C 13 DFFE + 0 2 0 4 cnt12 (:14)
- 1 - C 12 DFFE + 0 2 0 2 cnt11 (:15)
- 3 - C 12 DFFE + 0 3 0 3 cnt10 (:16)
- 4 - C 12 DFFE + 0 2 0 4 cnt9 (:17)
- 7 - C 12 DFFE + 0 3 0 2 cnt8 (:18)
- 6 - C 12 DFFE + 0 2 0 3 cnt7 (:19)
- 7 - C 19 DFFE + 0 3 0 1 cnt6 (:20)
- 8 - C 19 DFFE + 0 2 0 2 cnt5 (:21)
- 6 - C 19 DFFE + 0 2 0 1 cnt4 (:22)
- 4 - C 19 DFFE + 0 3 0 1 cnt3 (:23)
- 5 - C 19 DFFE + 0 2 0 2 cnt2 (:24)
- 6 - C 16 DFFE + 0 2 0 1 cnt1 (:25)
- 5 - C 16 DFFE + 0 1 0 2 cnt0 (:26)
- 2 - C 06 OR2 s 0 4 0 1 ~50~1
- 1 - C 06 OR2 0 4 0 22 :50
- 1 - C 13 AND2 s 0 4 0 1 ~77~1
- 8 - C 13 OR2 0 4 0 1 :77
- 8 - C 12 AND2 s 0 3 0 1 ~102~1
- 2 - C 19 OR2 0 3 0 4 :120
- 3 - G 01 DFFE + 0 3 0 1 cnt114 (:399)
- 8 - G 01 DFFE + 0 2 0 2 cnt113 (:400)
- 7 - G 01 DFFE + 0 2 0 2 cnt112 (:401)
- 6 - G 01 DFFE + 0 3 0 3 cnt111 (:402)
- 5 - G 01 DFFE + 0 2 0 4 cnt110 (:403)
- 4 - G 17 DFFE + 0 2 0 2 cnt19~147 (:404)
- 8 - G 08 DFFE + 0 3 0 3 cnt18~147 (:405)
- 3 - G 17 DFFE + 0 2 0 4 cnt17~147 (:406)
- 7 - G 08 DFFE + 0 3 0 2 cnt16~147 (:407)
- 6 - G 08 DFFE + 0 2 0 3 cnt15~147 (:408)
- 1 - G 19 DFFE + 0 2 0 2 cnt14~147 (:409)
- 7 - G 19 DFFE + 0 3 0 1 cnt13~147 (:410)
- 8 - G 19 DFFE + 0 2 0 2 cnt12~147 (:411)
- 5 - G 19 DFFE + 0 2 0 1 cnt11~147 (:412)
- 3 - G 19 DFFE + 0 1 0 2 cnt10~147 (:413)
- 2 - G 01 OR2 0 4 0 16 :431
- 2 - G 17 OR2 s 0 3 0 1 ~446~1
- 2 - G 08 OR2 0 4 0 1 :446
- 5 - G 08 AND2 s 0 3 0 1 ~458~1
- 6 - G 19 OR2 0 2 0 3 :481
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\论文\taxi1\fen.rpt
fen
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 13/208( 6%) 1/104( 0%) 0/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 13/208( 6%) 1/104( 0%) 0/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
51: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\论文\taxi1\fen.rpt
fen
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 38 clk
Device-Specific Information: f:\论文\taxi1\fen.rpt
fen
** EQUATIONS **
clk : INPUT;
-- Node name is ':5' = 'a'
-- Equation name is 'a', location is LC1_G17, type is buried.
a = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !a & !_LC2_G1
# a & _LC2_G1;
-- Node name is ':4' = 'b'
-- Equation name is 'b', location is LC8_C16, type is buried.
b = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !b & !_LC1_C6
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