hostcont.v

sdram控制的内核

// since the write can be queued, but since all reads are blocked, the latch
// will not latch the addx on reads.  
assign reg_mp_addx = mp_addx;


//
// DECODED DQM LATCH
// generate the proper DQM[3:0] masks based on the address and on the mp_size 
//
always @(do_write or sys_rst_l or mp_addx or mp_size)
    // 32 bit masks
    // all masks are enabled (LOW)
    if (mp_size==2'b00)
       decoded_dqm <= 4'h0;
    // 16 bit masks
    // enable the masks accorsing to the half-word selected
    else if (mp_size==2'b10)
       case (mp_addx[1])
          `LO:      decoded_dqm <= 4'b1100;     // lower half-word enabled
           default: decoded_dqm <= 4'b0011;     // upper half-word enabled
       endcase
    // 8 bit masks
    // enablethe masks according to the byte specified.
    else if (mp_size==2'b01)
       case (mp_addx[1:0])
       2'b00:   decoded_dqm <= 4'b1110;
       2'b01:   decoded_dqm <= 4'b1101;
       2'b10:   decoded_dqm <= 4'b1011;
           default: decoded_dqm <= 4'b0111;
       endcase
    else
        decoded_dqm <= 4'bxxxx;


// MP DATA LATCH
// Used to hold the data from the micro.  Latch on the rising edge
// of mp_wr_l
//
`ifdef align_data_bus
always @(mp_data_in or reg_mp_addx)
    // 32 bit writes
    if (mp_size==2'b00)
       reg_mp_data <= mp_data_in;
    // 16 bit writes
    else if (mp_size==2'b10) 
       case(reg_mp_addx[1]) 
            `LO:     reg_mp_data[15:0] <= mp_data_in[15:0];
            default: reg_mp_data[31:16] <= mp_data_in[15:0];
       endcase
    // 8 bit writes
    else if (mp_size==2'b01)
       case(reg_mp_addx[1:0])
            2'b00:   reg_mp_data[7:0]   <= mp_data_in[7:0];
            2'b01:   reg_mp_data[15:8]  <= mp_data_in[7:0];
            2'b10:   reg_mp_data[23:16] <= mp_data_in[7:0];
            default: reg_mp_data[31:24] <= mp_data_in[7:0];
       endcase
//---------------------------------- if data aligning is not desired -------------------
`else
always @(mp_data_in)
     reg_mp_data <= mp_data_in;
`endif


//
// MODE REG REG
//
`define default_mode_reg {4'b0000,`default_mode_reg_CAS_LATENCY,`defulat_mode_reg_BURST_TYPE,`default_mode_reg_BURST_LENGHT}
always @(posedge sys_clk or negedge sys_rst_l)
    if (~sys_rst_l)
        reg_modeset <= 10'h000;
    else
    if (pwrup)
        reg_modeset <= `default_mode_reg;
    else 
    if (~sdram_mode_set_l & ~mp_cs_l & ~mp_wr_l)
        reg_modeset <= mp_data_in[10:0];

// SD DATA REGISTER
// This register holds in the data from the SDRAM
//
always @(posedge sys_clk or negedge sys_rst_l)
  if (~sys_rst_l)
    reg_sd_data <= 32'h00000000;
  else if (sd_rd_ena)
    reg_sd_data <= sd_data_buff;


//
// SD DATA BUS BUFFERS
//
assign sd_data_out  = reg_mp_data;
assign sd_data_buff = sd_data_in;



// SDRAM SIDE ADDX
always @(sd_addx10_mux or reg_mp_data or reg_mp_addx or reg_modeset)
  case (sd_addx10_mux)
    2'b00:   sd_addx[10] <= reg_mp_addx[20];
    2'b01:   sd_addx[10] <= 1'b0;
    2'b10:   sd_addx[10] <= reg_modeset[10];
    default: sd_addx[10] <= 1'b1;
  endcase

always @(sd_addx_mux or reg_modeset or reg_mp_addx)
  case (sd_addx_mux)
    2'b00:   sd_addx[9:0] <= reg_mp_addx[19:10];               // ROW
    2'b01:   sd_addx[9:0] <= {2'b00, reg_mp_addx[9:2]};        // COLUMN
    2'b10:   sd_addx[9:0] <= reg_modeset[9:0];
    default: sd_addx[9:0] <= 10'h000;
  endcase


// SD_BA
always @(sd_addx_mux or reg_mp_addx)
  case (sd_addx_mux)
    2'b00:    sd_ba <= reg_mp_addx[22:21];     
    2'b01:    sd_ba <= reg_mp_addx[22:21]; 
    default:  sd_ba <= 2'b00;
  endcase



// Micro data mux
assign reg_mp_data_mux = mp_data_mux ? 32'h00000000 : reg_mp_data;

// MP_DATA_OUT mux
// ------------------------------- do this only if the DATA aligning is desired -------
`ifdef align_data_bus
always @(mp_size or reg_sd_data or mp_addx)
  case (mp_size)
     // 32 bit reads
     2'b00:  
         mp_data_out <= reg_sd_data;
     // 16 bit reads
     2'b10:
         if (mp_addx[1])
            mp_data_out[15:0] <= reg_sd_data[31:16];
         else
            mp_data_out[15:0] <= reg_sd_data[15:0];
     // 8 bit reads
     default:
         case (mp_addx[1:0])
             2'b00:   mp_data_out[7:0] <= reg_sd_data[7:0];
             2'b01:   mp_data_out[7:0] <= reg_sd_data[15:0];
             2'b10:   mp_data_out[7:0] <= reg_sd_data[23:16];
             default: mp_data_out[7:0] <= reg_sd_data[31:24];
         endcase
  endcase       
`else
//---------------------------------- if data aligning is not desired -------------------
always @(reg_sd_data)
  mp_data_out <= reg_sd_data;
`endif

//
// DO_READ   DO_WRITE   DO_MODESET
// signal generation
//

always @(posedge sys_clk or negedge sys_rst_l)
  if (~sys_rst_l) begin
    do_read  <= `LO;
    do_write <= `LO;
    do_modeset <= `LO;
    do_state <= 3'b000;
    busy_a_ena <= `HI; 
  end
  else 
    case (do_state)
        // hang in here until a read or write is requested 
        // (mp_rd_l = 1'b0) or (mp_wr_l = 1'b0)
        3'b000: begin
            // a read request
            if (~mp_rd_l & ~mp_cs_l) begin          
                do_read <= `HI;
                do_state <= 3'b001;
            end
            // a write request
            else if (~mp_wr_l & ~mp_cs_l & sdram_mode_set_l) begin
                do_write <= `HI;
                do_state <= 3'b001;
            end
            // a mode set request
            else if (~mp_wr_l & ~mp_cs_l & ~sdram_mode_set_l) begin
                do_modeset <= `HI;
                do_state <= 3'b001;
            end
            else
                do_state <= 3'b000;         
        end
        
        // This cycle is dummy cycle.  Just to extend 'busy_ena_a' 
        // to a total of 2 cycles 
        3'b001:
            begin
                busy_a_ena <= `LO;      // disable busy_a generation
                if (do_write)
                   do_state <= 3'b011;
                else if (do_read)
                   do_state <= 3'b010;
                else if (do_modeset)
                   do_state <= 3'b110;
                else 
                   do_state <= 3'b001;
            end

        // hang in here until the sdramcnt has acknowledged the
        // read
        3'b010:
            if (do_read_ack) begin
                do_read <= `LO;
                do_state <= 3'b100;
            end
            else
                do_state <= 3'b010;

        // hang in here until the sdramcnt has acknowledged the 
        // write
        3'b011:
            if (do_write_ack) begin
                do_write <= `LO;
                do_state <= 3'b101;
            end
            else
                do_state <= 3'b011;

        // wait in here until the host has read the data
        // (i.e. has raised its mp_rd_l high)
        3'b100:
            if (mp_rd_l) begin
                busy_a_ena <= `HI;      // re-enable busy_a generation
                do_state <= 3'b000;
            end
            else
                do_state <= 3'b100;
                
        // wait in here until the host has relinquieshed the write bus
        // (i.e. has raised its mp_wr_l high)
        3'b101:
            if (mp_wr_l) begin
                busy_a_ena <= `HI;      // re-enable busy_a generation
                do_state <= 3'b000;
            end
            else
                do_state <= 3'b101;

        // hang in here until the sdramcnt has acknowledged the 
        // mode set
        3'b110:
            if (do_modeset_ack) begin
                do_modeset <= `LO;
                do_state <= 3'b101;
            end else
                do_state <= 3'b110;


    endcase
                



endmodule