pipemult.tan.qmsg

来自「使用Quartus II 5.0开发指导手册」· QMSG 代码 · 共 10 行 · 第 1/4 页

{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 q\[15\] ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg0 7.582 ns memory " "Info: tco from clock \"clk1\" to destination pin \"q\[15\]\" through memory \"ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg0\" is 7.582 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.384 ns + Longest memory " "Info: + Longest clock path from clock \"clk1\" to source memory is 2.384 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk1 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { clk1 } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk1~clkctrl 2 COMB CLKCTRL_G3 81 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 81; COMB Node = 'clk1~clkctrl'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "0.343 ns" { clk1 clk1~clkctrl } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.471 ns) 2.384 ns ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg0 3 MEM M512_X24_Y22 16 " "Info: 3: + IC(0.716 ns) + CELL(0.471 ns) = 2.384 ns; Loc. = M512_X24_Y22; Fanout = 16; MEM Node = 'ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "1.187 ns" { clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.325 ns 55.58 % " "Info: Total cell delay = 1.325 ns ( 55.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns 44.42 % " "Info: Total interconnect delay = 1.059 ns ( 44.42 % )" {  } {  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.384 ns" { clk1 clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.384 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.343ns 0.716ns } { 0.000ns 0.854ns 0.000ns 0.471ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.140 ns + " "Info: + Micro clock to output delay of source is 0.140 ns" {  } { { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.058 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.058 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg0 1 MEM M512_X24_Y22 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X24_Y22; Fanout = 16; MEM Node = 'ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.793 ns) 1.793 ns ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|q_b\[15\] 2 MEM M512_X24_Y22 1 " "Info: 2: + IC(0.000 ns) + CELL(1.793 ns) = 1.793 ns; Loc. = M512_X24_Y22; Fanout = 1; MEM Node = 'ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|q_b\[15\]'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "1.793 ns" { ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[15] } "NODE_NAME" } "" } } { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.313 ns) + CELL(1.952 ns) 5.058 ns q\[15\] 3 PIN PIN_D8 0 " "Info: 3: + IC(1.313 ns) + CELL(1.952 ns) = 5.058 ns; Loc. = PIN_D8; Fanout = 0; PIN Node = 'q\[15\]'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "3.265 ns" { ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[15] q[15] } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 296 688 864 312 "q\[15..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.745 ns 74.04 % " "Info: Total cell delay = 3.745 ns ( 74.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.313 ns 25.96 % " "Info: Total interconnect delay = 1.313 ns ( 25.96 % )" {  } {  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "5.058 ns" { ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[15] q[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.058 ns" { ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[15] q[15] } { 0.000ns 0.000ns 1.313ns } { 0.000ns 1.793ns 1.952ns } } }  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.384 ns" { clk1 clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.384 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.343ns 0.716ns } { 0.000ns 0.854ns 0.000ns 0.471ns } } } { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "5.058 ns" { ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[15] q[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.058 ns" { ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[15] q[15] } { 0.000ns 0.000ns 1.313ns } { 0.000ns 1.793ns 1.952ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "ram:inst1\|ram_block~0 rdaddress\[0\] clk1 -2.219 ns register " "Info: th for register \"ram:inst1\|ram_block~0\" (data pin = \"rdaddress\[0\]\", clock pin = \"clk1\") is -2.219 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.491 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to destination register is 2.491 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk1 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { clk1 } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk1~clkctrl 2 COMB CLKCTRL_G3 81 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 81; COMB Node = 'clk1~clkctrl'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "0.343 ns" { clk1 clk1~clkctrl } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.676 ns) + CELL(0.618 ns) 2.491 ns ram:inst1\|ram_block~0 3 REG LCFF_X25_Y23_N13 1 " "Info: 3: + IC(0.676 ns) + CELL(0.618 ns) = 2.491 ns; Loc. = LCFF_X25_Y23_N13; Fanout = 1; REG Node = 'ram:inst1\|ram_block~0'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "1.294 ns" { clk1~clkctrl ram:inst1|ram_block~0 } "NODE_NAME" } "" } } { "ram.vhd" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/ram.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns 59.09 % " "Info: Total cell delay = 1.472 ns ( 59.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.019 ns 40.91 % " "Info: Total interconnect delay = 1.019 ns ( 40.91 % )" {  } {  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.491 ns" { clk1 clk1~clkctrl ram:inst1|ram_block~0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.491 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|ram_block~0 } { 0.000ns 0.000ns 0.343ns 0.676ns } { 0.000ns 0.854ns 0.000ns 0.618ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "ram.vhd" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/ram.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.859 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.859 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.772 ns) 0.772 ns rdaddress\[0\] 1 PIN PIN_A10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.772 ns) = 0.772 ns; Loc. = PIN_A10; Fanout = 1; PIN Node = 'rdaddress\[0\]'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { rdaddress[0] } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 344 320 488 360 "rdaddress\[4..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.778 ns) + CELL(0.309 ns) 4.859 ns ram:inst1\|ram_block~0 2 REG LCFF_X25_Y23_N13 1 " "Info: 2: + IC(3.778 ns) + CELL(0.309 ns) = 4.859 ns; Loc. = LCFF_X25_Y23_N13; Fanout = 1; REG Node = 'ram:inst1\|ram_block~0'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "4.087 ns" { rdaddress[0] ram:inst1|ram_block~0 } "NODE_NAME" } "" } } { "ram.vhd" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/ram.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.081 ns 22.25 % " "Info: Total cell delay = 1.081 ns ( 22.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.778 ns 77.75 % " "Info: Total interconnect delay = 3.778 ns ( 77.75 % )" {  } {  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "4.859 ns" { rdaddress[0] ram:inst1|ram_block~0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.859 ns" { rdaddress[0] rdaddress[0]~combout ram:inst1|ram_block~0 } { 0.000ns 0.000ns 3.778ns } { 0.000ns 0.772ns 0.309ns } } }  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.491 ns" { clk1 clk1~clkctrl ram:inst1|ram_block~0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.491 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|ram_block~0 } { 0.000ns 0.000ns 0.343ns 0.676ns } { 0.000ns 0.854ns 0.000ns 0.618ns } } } { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "4.859 ns" { rdaddress[0] ram:inst1|ram_block~0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.859 ns" { rdaddress[0] rdaddress[0]~combout ram:inst1|ram_block~0 } { 0.000ns 0.000ns 3.778ns } { 0.000ns 0.772ns 0.309ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 27 17:03:29 2005 " "Info: Processing ended: Fri May 27 17:03:29 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}