pipemult.tan.qmsg

来自「使用Quartus II 5.0开发指导手册」· QMSG 代码 · 共 10 行 · 第 1/4 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register mult:inst\|lpm_mult:lpm_mult_component\|mult_edq:auto_generated\|mac_mult2~DATAOUT2 memory ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~porta_datain_reg2 469.04 MHz 2.132 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 469.04 MHz between source register \"mult:inst\|lpm_mult:lpm_mult_component\|mult_edq:auto_generated\|mac_mult2~DATAOUT2\" and destination memory \"ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~porta_datain_reg2\" (period= 2.132 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.805 ns + Longest register memory " "Info: + Longest register to memory delay is 1.805 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 0.190 ns mult:inst\|lpm_mult:lpm_mult_component\|mult_edq:auto_generated\|mac_mult2~DATAOUT2 1 REG DSPMULT_X28_Y22_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.190 ns) = 0.190 ns; Loc. = DSPMULT_X28_Y22_N0; Fanout = 1; REG Node = 'mult:inst\|lpm_mult:lpm_mult_component\|mult_edq:auto_generated\|mac_mult2~DATAOUT2'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2 } "NODE_NAME" } "" } } { "db/mult_edq.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/mult_edq.tdf" 44 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 0.790 ns mult:inst\|lpm_mult:lpm_mult_component\|mult_edq:auto_generated\|result\[2\] 2 COMB DSPOUT_X28_Y22_N2 1 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 0.790 ns; Loc. = DSPOUT_X28_Y22_N2; Fanout = 1; COMB Node = 'mult:inst\|lpm_mult:lpm_mult_component\|mult_edq:auto_generated\|result\[2\]'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "0.600 ns" { mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2 mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[2] } "NODE_NAME" } "" } } { "db/mult_edq.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/mult_edq.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.881 ns) + CELL(0.134 ns) 1.805 ns ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~porta_datain_reg2 3 MEM M512_X24_Y22 1 " "Info: 3: + IC(0.881 ns) + CELL(0.134 ns) = 1.805 ns; Loc. = M512_X24_Y22; Fanout = 1; MEM Node = 'ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~porta_datain_reg2'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "1.015 ns" { mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[2] ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg2 } "NODE_NAME" } "" } } { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.924 ns 51.19 % " "Info: Total cell delay = 0.924 ns ( 51.19 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.881 ns 48.81 % " "Info: Total interconnect delay = 0.881 ns ( 48.81 % )" {  } {  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "1.805 ns" { mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2 mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[2] ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.805 ns" { mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2 mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[2] ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg2 } { 0.000ns 0.000ns 0.881ns } { 0.190ns 0.600ns 0.134ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.305 ns - Smallest " "Info: - Smallest clock skew is -0.305 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.372 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk1\" to destination memory is 2.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk1 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { clk1 } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk1~clkctrl 2 COMB CLKCTRL_G3 81 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 81; COMB Node = 'clk1~clkctrl'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "0.343 ns" { clk1 clk1~clkctrl } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.459 ns) 2.372 ns ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~porta_datain_reg2 3 MEM M512_X24_Y22 1 " "Info: 3: + IC(0.716 ns) + CELL(0.459 ns) = 2.372 ns; Loc. = M512_X24_Y22; Fanout = 1; MEM Node = 'ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~porta_datain_reg2'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "1.175 ns" { clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg2 } "NODE_NAME" } "" } } { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.313 ns 55.35 % " "Info: Total cell delay = 1.313 ns ( 55.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns 44.65 % " "Info: Total interconnect delay = 1.059 ns ( 44.65 % )" {  } {  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.372 ns" { clk1 clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.372 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg2 } { 0.000ns 0.000ns 0.343ns 0.716ns } { 0.000ns 0.854ns 0.000ns 0.459ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.677 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 2.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk1 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { clk1 } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk1~clkctrl 2 COMB CLKCTRL_G3 81 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 81; COMB Node = 'clk1~clkctrl'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "0.343 ns" { clk1 clk1~clkctrl } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(0.780 ns) 2.677 ns mult:inst\|lpm_mult:lpm_mult_component\|mult_edq:auto_generated\|mac_mult2~DATAOUT2 3 REG DSPMULT_X28_Y22_N0 1 " "Info: 3: + IC(0.700 ns) + CELL(0.780 ns) = 2.677 ns; Loc. = DSPMULT_X28_Y22_N0; Fanout = 1; REG Node = 'mult:inst\|lpm_mult:lpm_mult_component\|mult_edq:auto_generated\|mac_mult2~DATAOUT2'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "1.480 ns" { clk1~clkctrl mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2 } "NODE_NAME" } "" } } { "db/mult_edq.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/mult_edq.tdf" 44 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns 61.04 % " "Info: Total cell delay = 1.634 ns ( 61.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.043 ns 38.96 % " "Info: Total interconnect delay = 1.043 ns ( 38.96 % )" {  } {  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.677 ns" { clk1 clk1~clkctrl mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.677 ns" { clk1 clk1~combout clk1~clkctrl mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2 } { 0.000ns 0.000ns 0.343ns 0.700ns } { 0.000ns 0.854ns 0.000ns 0.780ns } } }  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.372 ns" { clk1 clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.372 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg2 } { 0.000ns 0.000ns 0.343ns 0.716ns } { 0.000ns 0.854ns 0.000ns 0.459ns } } } { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.677 ns" { clk1 clk1~clkctrl mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.677 ns" { clk1 clk1~combout clk1~clkctrl mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2 } { 0.000ns 0.000ns 0.343ns 0.700ns } { 0.000ns 0.854ns 0.000ns 0.780ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "db/mult_edq.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/mult_edq.tdf" 44 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.022 ns + " "Info: + Micro setup delay of destination is 0.022 ns" {  } { { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "1.805 ns" { mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2 mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[2] ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.805 ns" { mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2 mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[2] ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg2 } { 0.000ns 0.000ns 0.881ns } { 0.190ns 0.600ns 0.134ns } } } { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.372 ns" { clk1 clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.372 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg2 } { 0.000ns 0.000ns 0.343ns 0.716ns } { 0.000ns 0.854ns 0.000ns 0.459ns } } } { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.677 ns" { clk1 clk1~clkctrl mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.677 ns" { clk1 clk1~combout clk1~clkctrl mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2 } { 0.000ns 0.000ns 0.343ns 0.700ns } { 0.000ns 0.854ns 0.000ns 0.780ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~porta_datain_reg0 wren clk1 3.212 ns memory " "Info: tsu for memory \"ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~porta_datain_reg0\" (data pin = \"wren\", clock pin = \"clk1\") is 3.212 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.562 ns + Longest pin memory " "Info: + Longest pin to memory delay is 5.562 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.799 ns) 0.799 ns wren 1 PIN PIN_D13 21 " "Info: 1: + IC(0.000 ns) + CELL(0.799 ns) = 0.799 ns; Loc. = PIN_D13; Fanout = 21; PIN Node = 'wren'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { wren } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 360 320 488 376 "wren" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.322 ns) + CELL(0.441 ns) 5.562 ns ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~porta_datain_reg0 2 MEM M512_X24_Y22 1 " "Info: 2: + IC(4.322 ns) + CELL(0.441 ns) = 5.562 ns; Loc. = M512_X24_Y22; Fanout = 1; MEM Node = 'ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "4.763 ns" { wren ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.240 ns 22.29 % " "Info: Total cell delay = 1.240 ns ( 22.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.322 ns 77.71 % " "Info: Total interconnect delay = 4.322 ns ( 77.71 % )" {  } {  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "5.562 ns" { wren ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.562 ns" { wren wren~combout ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 4.322ns } { 0.000ns 0.799ns 0.441ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.022 ns + " "Info: + Micro setup delay of destination is 0.022 ns" {  } { { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.372 ns - Shortest memory " "Info: - Shortest clock path from clock \"clk1\" to destination memory is 2.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk1 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { clk1 } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk1~clkctrl 2 COMB CLKCTRL_G3 81 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 81; COMB Node = 'clk1~clkctrl'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "0.343 ns" { clk1 clk1~clkctrl } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.459 ns) 2.372 ns ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~porta_datain_reg0 3 MEM M512_X24_Y22 1 " "Info: 3: + IC(0.716 ns) + CELL(0.459 ns) = 2.372 ns; Loc. = M512_X24_Y22; Fanout = 1; MEM Node = 'ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "1.175 ns" { clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.313 ns 55.35 % " "Info: Total cell delay = 1.313 ns ( 55.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns 44.65 % " "Info: Total interconnect delay = 1.059 ns ( 44.65 % )" {  } {  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.372 ns" { clk1 clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.372 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 0.343ns 0.716ns } { 0.000ns 0.854ns 0.000ns 0.459ns } } }  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "5.562 ns" { wren ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.562 ns" { wren wren~combout ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 4.322ns } { 0.000ns 0.799ns 0.441ns } } } { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.372 ns" { clk1 clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.372 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 0.343ns 0.716ns } { 0.000ns 0.854ns 0.000ns 0.459ns } } }  } 0}