pipemult.map.eqn

来自「使用Quartus II 5.0开发指导手册」· EQN 代码 · 共 760 行 · 第 1/3 页

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- applicable agreement for further details.
--G1_q_b[15] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[15]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[15]_PORT_A_data_in = E1_result[15];
G1_q_b[15]_PORT_A_data_in_reg = DFFE(G1_q_b[15]_PORT_A_data_in, G1_q_b[15]_clock_0, , , G1_q_b[15]_clock_enable_0);
G1_q_b[15]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[15]_PORT_A_address_reg = DFFE(G1_q_b[15]_PORT_A_address, G1_q_b[15]_clock_0, , , G1_q_b[15]_clock_enable_0);
G1_q_b[15]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[15]_PORT_B_address_reg = DFFE(G1_q_b[15]_PORT_B_address, G1_q_b[15]_clock_1, , , );
G1_q_b[15]_PORT_A_write_enable = VCC;
G1_q_b[15]_PORT_A_write_enable_reg = DFFE(G1_q_b[15]_PORT_A_write_enable, G1_q_b[15]_clock_0, , , G1_q_b[15]_clock_enable_0);
G1_q_b[15]_PORT_B_read_enable = VCC;
G1_q_b[15]_PORT_B_read_enable_reg = DFFE(G1_q_b[15]_PORT_B_read_enable, G1_q_b[15]_clock_1, , , );
G1_q_b[15]_clock_0 = clk1;
G1_q_b[15]_clock_1 = clk1;
G1_q_b[15]_clock_enable_0 = wren;
G1_q_b[15]_PORT_B_data_out = MEMORY(G1_q_b[15]_PORT_A_data_in_reg, , G1_q_b[15]_PORT_A_address_reg, G1_q_b[15]_PORT_B_address_reg, G1_q_b[15]_PORT_A_write_enable_reg, G1_q_b[15]_PORT_B_read_enable_reg, , , G1_q_b[15]_clock_0, G1_q_b[15]_clock_1, G1_q_b[15]_clock_enable_0, , , );
G1_q_b[15] = G1_q_b[15]_PORT_B_data_out[0];


--G1_q_b[14] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[14]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[14]_PORT_A_data_in = E1_result[14];
G1_q_b[14]_PORT_A_data_in_reg = DFFE(G1_q_b[14]_PORT_A_data_in, G1_q_b[14]_clock_0, , , G1_q_b[14]_clock_enable_0);
G1_q_b[14]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[14]_PORT_A_address_reg = DFFE(G1_q_b[14]_PORT_A_address, G1_q_b[14]_clock_0, , , G1_q_b[14]_clock_enable_0);
G1_q_b[14]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[14]_PORT_B_address_reg = DFFE(G1_q_b[14]_PORT_B_address, G1_q_b[14]_clock_1, , , );
G1_q_b[14]_PORT_A_write_enable = VCC;
G1_q_b[14]_PORT_A_write_enable_reg = DFFE(G1_q_b[14]_PORT_A_write_enable, G1_q_b[14]_clock_0, , , G1_q_b[14]_clock_enable_0);
G1_q_b[14]_PORT_B_read_enable = VCC;
G1_q_b[14]_PORT_B_read_enable_reg = DFFE(G1_q_b[14]_PORT_B_read_enable, G1_q_b[14]_clock_1, , , );
G1_q_b[14]_clock_0 = clk1;
G1_q_b[14]_clock_1 = clk1;
G1_q_b[14]_clock_enable_0 = wren;
G1_q_b[14]_PORT_B_data_out = MEMORY(G1_q_b[14]_PORT_A_data_in_reg, , G1_q_b[14]_PORT_A_address_reg, G1_q_b[14]_PORT_B_address_reg, G1_q_b[14]_PORT_A_write_enable_reg, G1_q_b[14]_PORT_B_read_enable_reg, , , G1_q_b[14]_clock_0, G1_q_b[14]_clock_1, G1_q_b[14]_clock_enable_0, , , );
G1_q_b[14] = G1_q_b[14]_PORT_B_data_out[0];


--G1_q_b[13] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[13]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[13]_PORT_A_data_in = E1_result[13];
G1_q_b[13]_PORT_A_data_in_reg = DFFE(G1_q_b[13]_PORT_A_data_in, G1_q_b[13]_clock_0, , , G1_q_b[13]_clock_enable_0);
G1_q_b[13]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[13]_PORT_A_address_reg = DFFE(G1_q_b[13]_PORT_A_address, G1_q_b[13]_clock_0, , , G1_q_b[13]_clock_enable_0);
G1_q_b[13]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[13]_PORT_B_address_reg = DFFE(G1_q_b[13]_PORT_B_address, G1_q_b[13]_clock_1, , , );
G1_q_b[13]_PORT_A_write_enable = VCC;
G1_q_b[13]_PORT_A_write_enable_reg = DFFE(G1_q_b[13]_PORT_A_write_enable, G1_q_b[13]_clock_0, , , G1_q_b[13]_clock_enable_0);
G1_q_b[13]_PORT_B_read_enable = VCC;
G1_q_b[13]_PORT_B_read_enable_reg = DFFE(G1_q_b[13]_PORT_B_read_enable, G1_q_b[13]_clock_1, , , );
G1_q_b[13]_clock_0 = clk1;
G1_q_b[13]_clock_1 = clk1;
G1_q_b[13]_clock_enable_0 = wren;
G1_q_b[13]_PORT_B_data_out = MEMORY(G1_q_b[13]_PORT_A_data_in_reg, , G1_q_b[13]_PORT_A_address_reg, G1_q_b[13]_PORT_B_address_reg, G1_q_b[13]_PORT_A_write_enable_reg, G1_q_b[13]_PORT_B_read_enable_reg, , , G1_q_b[13]_clock_0, G1_q_b[13]_clock_1, G1_q_b[13]_clock_enable_0, , , );
G1_q_b[13] = G1_q_b[13]_PORT_B_data_out[0];


--G1_q_b[12] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[12]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[12]_PORT_A_data_in = E1_result[12];
G1_q_b[12]_PORT_A_data_in_reg = DFFE(G1_q_b[12]_PORT_A_data_in, G1_q_b[12]_clock_0, , , G1_q_b[12]_clock_enable_0);
G1_q_b[12]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[12]_PORT_A_address_reg = DFFE(G1_q_b[12]_PORT_A_address, G1_q_b[12]_clock_0, , , G1_q_b[12]_clock_enable_0);
G1_q_b[12]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[12]_PORT_B_address_reg = DFFE(G1_q_b[12]_PORT_B_address, G1_q_b[12]_clock_1, , , );
G1_q_b[12]_PORT_A_write_enable = VCC;
G1_q_b[12]_PORT_A_write_enable_reg = DFFE(G1_q_b[12]_PORT_A_write_enable, G1_q_b[12]_clock_0, , , G1_q_b[12]_clock_enable_0);
G1_q_b[12]_PORT_B_read_enable = VCC;
G1_q_b[12]_PORT_B_read_enable_reg = DFFE(G1_q_b[12]_PORT_B_read_enable, G1_q_b[12]_clock_1, , , );
G1_q_b[12]_clock_0 = clk1;
G1_q_b[12]_clock_1 = clk1;
G1_q_b[12]_clock_enable_0 = wren;
G1_q_b[12]_PORT_B_data_out = MEMORY(G1_q_b[12]_PORT_A_data_in_reg, , G1_q_b[12]_PORT_A_address_reg, G1_q_b[12]_PORT_B_address_reg, G1_q_b[12]_PORT_A_write_enable_reg, G1_q_b[12]_PORT_B_read_enable_reg, , , G1_q_b[12]_clock_0, G1_q_b[12]_clock_1, G1_q_b[12]_clock_enable_0, , , );
G1_q_b[12] = G1_q_b[12]_PORT_B_data_out[0];


--G1_q_b[11] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[11]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[11]_PORT_A_data_in = E1_result[11];
G1_q_b[11]_PORT_A_data_in_reg = DFFE(G1_q_b[11]_PORT_A_data_in, G1_q_b[11]_clock_0, , , G1_q_b[11]_clock_enable_0);
G1_q_b[11]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[11]_PORT_A_address_reg = DFFE(G1_q_b[11]_PORT_A_address, G1_q_b[11]_clock_0, , , G1_q_b[11]_clock_enable_0);
G1_q_b[11]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[11]_PORT_B_address_reg = DFFE(G1_q_b[11]_PORT_B_address, G1_q_b[11]_clock_1, , , );
G1_q_b[11]_PORT_A_write_enable = VCC;
G1_q_b[11]_PORT_A_write_enable_reg = DFFE(G1_q_b[11]_PORT_A_write_enable, G1_q_b[11]_clock_0, , , G1_q_b[11]_clock_enable_0);
G1_q_b[11]_PORT_B_read_enable = VCC;
G1_q_b[11]_PORT_B_read_enable_reg = DFFE(G1_q_b[11]_PORT_B_read_enable, G1_q_b[11]_clock_1, , , );
G1_q_b[11]_clock_0 = clk1;
G1_q_b[11]_clock_1 = clk1;
G1_q_b[11]_clock_enable_0 = wren;
G1_q_b[11]_PORT_B_data_out = MEMORY(G1_q_b[11]_PORT_A_data_in_reg, , G1_q_b[11]_PORT_A_address_reg, G1_q_b[11]_PORT_B_address_reg, G1_q_b[11]_PORT_A_write_enable_reg, G1_q_b[11]_PORT_B_read_enable_reg, , , G1_q_b[11]_clock_0, G1_q_b[11]_clock_1, G1_q_b[11]_clock_enable_0, , , );
G1_q_b[11] = G1_q_b[11]_PORT_B_data_out[0];


--G1_q_b[10] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[10]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[10]_PORT_A_data_in = E1_result[10];
G1_q_b[10]_PORT_A_data_in_reg = DFFE(G1_q_b[10]_PORT_A_data_in, G1_q_b[10]_clock_0, , , G1_q_b[10]_clock_enable_0);
G1_q_b[10]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[10]_PORT_A_address_reg = DFFE(G1_q_b[10]_PORT_A_address, G1_q_b[10]_clock_0, , , G1_q_b[10]_clock_enable_0);
G1_q_b[10]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[10]_PORT_B_address_reg = DFFE(G1_q_b[10]_PORT_B_address, G1_q_b[10]_clock_1, , , );
G1_q_b[10]_PORT_A_write_enable = VCC;
G1_q_b[10]_PORT_A_write_enable_reg = DFFE(G1_q_b[10]_PORT_A_write_enable, G1_q_b[10]_clock_0, , , G1_q_b[10]_clock_enable_0);
G1_q_b[10]_PORT_B_read_enable = VCC;
G1_q_b[10]_PORT_B_read_enable_reg = DFFE(G1_q_b[10]_PORT_B_read_enable, G1_q_b[10]_clock_1, , , );
G1_q_b[10]_clock_0 = clk1;
G1_q_b[10]_clock_1 = clk1;
G1_q_b[10]_clock_enable_0 = wren;
G1_q_b[10]_PORT_B_data_out = MEMORY(G1_q_b[10]_PORT_A_data_in_reg, , G1_q_b[10]_PORT_A_address_reg, G1_q_b[10]_PORT_B_address_reg, G1_q_b[10]_PORT_A_write_enable_reg, G1_q_b[10]_PORT_B_read_enable_reg, , , G1_q_b[10]_clock_0, G1_q_b[10]_clock_1, G1_q_b[10]_clock_enable_0, , , );
G1_q_b[10] = G1_q_b[10]_PORT_B_data_out[0];


--G1_q_b[9] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[9]_PORT_A_data_in = E1_result[9];
G1_q_b[9]_PORT_A_data_in_reg = DFFE(G1_q_b[9]_PORT_A_data_in, G1_q_b[9]_clock_0, , , G1_q_b[9]_clock_enable_0);
G1_q_b[9]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[9]_PORT_A_address_reg = DFFE(G1_q_b[9]_PORT_A_address, G1_q_b[9]_clock_0, , , G1_q_b[9]_clock_enable_0);
G1_q_b[9]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[9]_PORT_B_address_reg = DFFE(G1_q_b[9]_PORT_B_address, G1_q_b[9]_clock_1, , , );
G1_q_b[9]_PORT_A_write_enable = VCC;
G1_q_b[9]_PORT_A_write_enable_reg = DFFE(G1_q_b[9]_PORT_A_write_enable, G1_q_b[9]_clock_0, , , G1_q_b[9]_clock_enable_0);
G1_q_b[9]_PORT_B_read_enable = VCC;
G1_q_b[9]_PORT_B_read_enable_reg = DFFE(G1_q_b[9]_PORT_B_read_enable, G1_q_b[9]_clock_1, , , );
G1_q_b[9]_clock_0 = clk1;
G1_q_b[9]_clock_1 = clk1;
G1_q_b[9]_clock_enable_0 = wren;
G1_q_b[9]_PORT_B_data_out = MEMORY(G1_q_b[9]_PORT_A_data_in_reg, , G1_q_b[9]_PORT_A_address_reg, G1_q_b[9]_PORT_B_address_reg, G1_q_b[9]_PORT_A_write_enable_reg, G1_q_b[9]_PORT_B_read_enable_reg, , , G1_q_b[9]_clock_0, G1_q_b[9]_clock_1, G1_q_b[9]_clock_enable_0, , , );
G1_q_b[9] = G1_q_b[9]_PORT_B_data_out[0];


--G1_q_b[8] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[8]_PORT_A_data_in = E1_result[8];
G1_q_b[8]_PORT_A_data_in_reg = DFFE(G1_q_b[8]_PORT_A_data_in, G1_q_b[8]_clock_0, , , G1_q_b[8]_clock_enable_0);
G1_q_b[8]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[8]_PORT_A_address_reg = DFFE(G1_q_b[8]_PORT_A_address, G1_q_b[8]_clock_0, , , G1_q_b[8]_clock_enable_0);
G1_q_b[8]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[8]_PORT_B_address_reg = DFFE(G1_q_b[8]_PORT_B_address, G1_q_b[8]_clock_1, , , );
G1_q_b[8]_PORT_A_write_enable = VCC;
G1_q_b[8]_PORT_A_write_enable_reg = DFFE(G1_q_b[8]_PORT_A_write_enable, G1_q_b[8]_clock_0, , , G1_q_b[8]_clock_enable_0);
G1_q_b[8]_PORT_B_read_enable = VCC;
G1_q_b[8]_PORT_B_read_enable_reg = DFFE(G1_q_b[8]_PORT_B_read_enable, G1_q_b[8]_clock_1, , , );
G1_q_b[8]_clock_0 = clk1;
G1_q_b[8]_clock_1 = clk1;
G1_q_b[8]_clock_enable_0 = wren;
G1_q_b[8]_PORT_B_data_out = MEMORY(G1_q_b[8]_PORT_A_data_in_reg, , G1_q_b[8]_PORT_A_address_reg, G1_q_b[8]_PORT_B_address_reg, G1_q_b[8]_PORT_A_write_enable_reg, G1_q_b[8]_PORT_B_read_enable_reg, , , G1_q_b[8]_clock_0, G1_q_b[8]_clock_1, G1_q_b[8]_clock_enable_0, , , );
G1_q_b[8] = G1_q_b[8]_PORT_B_data_out[0];


--G1_q_b[7] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[7]_PORT_A_data_in = E1_result[7];
G1_q_b[7]_PORT_A_data_in_reg = DFFE(G1_q_b[7]_PORT_A_data_in, G1_q_b[7]_clock_0, , , G1_q_b[7]_clock_enable_0);
G1_q_b[7]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[7]_PORT_A_address_reg = DFFE(G1_q_b[7]_PORT_A_address, G1_q_b[7]_clock_0, , , G1_q_b[7]_clock_enable_0);
G1_q_b[7]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[7]_PORT_B_address_reg = DFFE(G1_q_b[7]_PORT_B_address, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_write_enable = VCC;
G1_q_b[7]_PORT_A_write_enable_reg = DFFE(G1_q_b[7]_PORT_A_write_enable, G1_q_b[7]_clock_0, , , G1_q_b[7]_clock_enable_0);
G1_q_b[7]_PORT_B_read_enable = VCC;
G1_q_b[7]_PORT_B_read_enable_reg = DFFE(G1_q_b[7]_PORT_B_read_enable, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_clock_0 = clk1;
G1_q_b[7]_clock_1 = clk1;
G1_q_b[7]_clock_enable_0 = wren;
G1_q_b[7]_PORT_B_data_out = MEMORY(G1_q_b[7]_PORT_A_data_in_reg, , G1_q_b[7]_PORT_A_address_reg, G1_q_b[7]_PORT_B_address_reg, G1_q_b[7]_PORT_A_write_enable_reg, G1_q_b[7]_PORT_B_read_enable_reg, , , G1_q_b[7]_clock_0, G1_q_b[7]_clock_1, G1_q_b[7]_clock_enable_0, , , );
G1_q_b[7] = G1_q_b[7]_PORT_B_data_out[0];


--G1_q_b[6] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[6]_PORT_A_data_in = E1_result[6];
G1_q_b[6]_PORT_A_data_in_reg = DFFE(G1_q_b[6]_PORT_A_data_in, G1_q_b[6]_clock_0, , , G1_q_b[6]_clock_enable_0);
G1_q_b[6]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[6]_PORT_A_address_reg = DFFE(G1_q_b[6]_PORT_A_address, G1_q_b[6]_clock_0, , , G1_q_b[6]_clock_enable_0);
G1_q_b[6]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[6]_PORT_B_address_reg = DFFE(G1_q_b[6]_PORT_B_address, G1_q_b[6]_clock_1, , , );
G1_q_b[6]_PORT_A_write_enable = VCC;
G1_q_b[6]_PORT_A_write_enable_reg = DFFE(G1_q_b[6]_PORT_A_write_enable, G1_q_b[6]_clock_0, , , G1_q_b[6]_clock_enable_0);
G1_q_b[6]_PORT_B_read_enable = VCC;
G1_q_b[6]_PORT_B_read_enable_reg = DFFE(G1_q_b[6]_PORT_B_read_enable, G1_q_b[6]_clock_1, , , );
G1_q_b[6]_clock_0 = clk1;
G1_q_b[6]_clock_1 = clk1;
G1_q_b[6]_clock_enable_0 = wren;
G1_q_b[6]_PORT_B_data_out = MEMORY(G1_q_b[6]_PORT_A_data_in_reg, , G1_q_b[6]_PORT_A_address_reg, G1_q_b[6]_PORT_B_address_reg, G1_q_b[6]_PORT_A_write_enable_reg, G1_q_b[6]_PORT_B_read_enable_reg, , , G1_q_b[6]_clock_0, G1_q_b[6]_clock_1, G1_q_b[6]_clock_enable_0, , , );
G1_q_b[6] = G1_q_b[6]_PORT_B_data_out[0];


--G1_q_b[5] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[5]_PORT_A_data_in = E1_result[5];
G1_q_b[5]_PORT_A_data_in_reg = DFFE(G1_q_b[5]_PORT_A_data_in, G1_q_b[5]_clock_0, , , G1_q_b[5]_clock_enable_0);
G1_q_b[5]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[5]_PORT_A_address_reg = DFFE(G1_q_b[5]_PORT_A_address, G1_q_b[5]_clock_0, , , G1_q_b[5]_clock_enable_0);
G1_q_b[5]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[5]_PORT_B_address_reg = DFFE(G1_q_b[5]_PORT_B_address, G1_q_b[5]_clock_1, , , );
G1_q_b[5]_PORT_A_write_enable = VCC;
G1_q_b[5]_PORT_A_write_enable_reg = DFFE(G1_q_b[5]_PORT_A_write_enable, G1_q_b[5]_clock_0, , , G1_q_b[5]_clock_enable_0);
G1_q_b[5]_PORT_B_read_enable = VCC;
G1_q_b[5]_PORT_B_read_enable_reg = DFFE(G1_q_b[5]_PORT_B_read_enable, G1_q_b[5]_clock_1, , , );
G1_q_b[5]_clock_0 = clk1;
G1_q_b[5]_clock_1 = clk1;
G1_q_b[5]_clock_enable_0 = wren;
G1_q_b[5]_PORT_B_data_out = MEMORY(G1_q_b[5]_PORT_A_data_in_reg, , G1_q_b[5]_PORT_A_address_reg, G1_q_b[5]_PORT_B_address_reg, G1_q_b[5]_PORT_A_write_enable_reg, G1_q_b[5]_PORT_B_read_enable_reg, , , G1_q_b[5]_clock_0, G1_q_b[5]_clock_1, G1_q_b[5]_clock_enable_0, , , );
G1_q_b[5] = G1_q_b[5]_PORT_B_data_out[0];