pipemult.map.eqn

来自「使用Quartus II 5.0开发指导手册」· EQN 代码 · 共 760 行 · 第 1/3 页

--G1_q_b[4] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[4]_PORT_A_data_in = E1_result[4];
G1_q_b[4]_PORT_A_data_in_reg = DFFE(G1_q_b[4]_PORT_A_data_in, G1_q_b[4]_clock_0, , , G1_q_b[4]_clock_enable_0);
G1_q_b[4]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[4]_PORT_A_address_reg = DFFE(G1_q_b[4]_PORT_A_address, G1_q_b[4]_clock_0, , , G1_q_b[4]_clock_enable_0);
G1_q_b[4]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[4]_PORT_B_address_reg = DFFE(G1_q_b[4]_PORT_B_address, G1_q_b[4]_clock_1, , , );
G1_q_b[4]_PORT_A_write_enable = VCC;
G1_q_b[4]_PORT_A_write_enable_reg = DFFE(G1_q_b[4]_PORT_A_write_enable, G1_q_b[4]_clock_0, , , G1_q_b[4]_clock_enable_0);
G1_q_b[4]_PORT_B_read_enable = VCC;
G1_q_b[4]_PORT_B_read_enable_reg = DFFE(G1_q_b[4]_PORT_B_read_enable, G1_q_b[4]_clock_1, , , );
G1_q_b[4]_clock_0 = clk1;
G1_q_b[4]_clock_1 = clk1;
G1_q_b[4]_clock_enable_0 = wren;
G1_q_b[4]_PORT_B_data_out = MEMORY(G1_q_b[4]_PORT_A_data_in_reg, , G1_q_b[4]_PORT_A_address_reg, G1_q_b[4]_PORT_B_address_reg, G1_q_b[4]_PORT_A_write_enable_reg, G1_q_b[4]_PORT_B_read_enable_reg, , , G1_q_b[4]_clock_0, G1_q_b[4]_clock_1, G1_q_b[4]_clock_enable_0, , , );
G1_q_b[4] = G1_q_b[4]_PORT_B_data_out[0];


--G1_q_b[3] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[3]_PORT_A_data_in = E1_result[3];
G1_q_b[3]_PORT_A_data_in_reg = DFFE(G1_q_b[3]_PORT_A_data_in, G1_q_b[3]_clock_0, , , G1_q_b[3]_clock_enable_0);
G1_q_b[3]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[3]_PORT_A_address_reg = DFFE(G1_q_b[3]_PORT_A_address, G1_q_b[3]_clock_0, , , G1_q_b[3]_clock_enable_0);
G1_q_b[3]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[3]_PORT_B_address_reg = DFFE(G1_q_b[3]_PORT_B_address, G1_q_b[3]_clock_1, , , );
G1_q_b[3]_PORT_A_write_enable = VCC;
G1_q_b[3]_PORT_A_write_enable_reg = DFFE(G1_q_b[3]_PORT_A_write_enable, G1_q_b[3]_clock_0, , , G1_q_b[3]_clock_enable_0);
G1_q_b[3]_PORT_B_read_enable = VCC;
G1_q_b[3]_PORT_B_read_enable_reg = DFFE(G1_q_b[3]_PORT_B_read_enable, G1_q_b[3]_clock_1, , , );
G1_q_b[3]_clock_0 = clk1;
G1_q_b[3]_clock_1 = clk1;
G1_q_b[3]_clock_enable_0 = wren;
G1_q_b[3]_PORT_B_data_out = MEMORY(G1_q_b[3]_PORT_A_data_in_reg, , G1_q_b[3]_PORT_A_address_reg, G1_q_b[3]_PORT_B_address_reg, G1_q_b[3]_PORT_A_write_enable_reg, G1_q_b[3]_PORT_B_read_enable_reg, , , G1_q_b[3]_clock_0, G1_q_b[3]_clock_1, G1_q_b[3]_clock_enable_0, , , );
G1_q_b[3] = G1_q_b[3]_PORT_B_data_out[0];


--G1_q_b[2] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[2]_PORT_A_data_in = E1_result[2];
G1_q_b[2]_PORT_A_data_in_reg = DFFE(G1_q_b[2]_PORT_A_data_in, G1_q_b[2]_clock_0, , , G1_q_b[2]_clock_enable_0);
G1_q_b[2]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[2]_PORT_A_address_reg = DFFE(G1_q_b[2]_PORT_A_address, G1_q_b[2]_clock_0, , , G1_q_b[2]_clock_enable_0);
G1_q_b[2]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[2]_PORT_B_address_reg = DFFE(G1_q_b[2]_PORT_B_address, G1_q_b[2]_clock_1, , , );
G1_q_b[2]_PORT_A_write_enable = VCC;
G1_q_b[2]_PORT_A_write_enable_reg = DFFE(G1_q_b[2]_PORT_A_write_enable, G1_q_b[2]_clock_0, , , G1_q_b[2]_clock_enable_0);
G1_q_b[2]_PORT_B_read_enable = VCC;
G1_q_b[2]_PORT_B_read_enable_reg = DFFE(G1_q_b[2]_PORT_B_read_enable, G1_q_b[2]_clock_1, , , );
G1_q_b[2]_clock_0 = clk1;
G1_q_b[2]_clock_1 = clk1;
G1_q_b[2]_clock_enable_0 = wren;
G1_q_b[2]_PORT_B_data_out = MEMORY(G1_q_b[2]_PORT_A_data_in_reg, , G1_q_b[2]_PORT_A_address_reg, G1_q_b[2]_PORT_B_address_reg, G1_q_b[2]_PORT_A_write_enable_reg, G1_q_b[2]_PORT_B_read_enable_reg, , , G1_q_b[2]_clock_0, G1_q_b[2]_clock_1, G1_q_b[2]_clock_enable_0, , , );
G1_q_b[2] = G1_q_b[2]_PORT_B_data_out[0];


--G1_q_b[1] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[1]_PORT_A_data_in = E1_result[1];
G1_q_b[1]_PORT_A_data_in_reg = DFFE(G1_q_b[1]_PORT_A_data_in, G1_q_b[1]_clock_0, , , G1_q_b[1]_clock_enable_0);
G1_q_b[1]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[1]_PORT_A_address_reg = DFFE(G1_q_b[1]_PORT_A_address, G1_q_b[1]_clock_0, , , G1_q_b[1]_clock_enable_0);
G1_q_b[1]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[1]_PORT_B_address_reg = DFFE(G1_q_b[1]_PORT_B_address, G1_q_b[1]_clock_1, , , );
G1_q_b[1]_PORT_A_write_enable = VCC;
G1_q_b[1]_PORT_A_write_enable_reg = DFFE(G1_q_b[1]_PORT_A_write_enable, G1_q_b[1]_clock_0, , , G1_q_b[1]_clock_enable_0);
G1_q_b[1]_PORT_B_read_enable = VCC;
G1_q_b[1]_PORT_B_read_enable_reg = DFFE(G1_q_b[1]_PORT_B_read_enable, G1_q_b[1]_clock_1, , , );
G1_q_b[1]_clock_0 = clk1;
G1_q_b[1]_clock_1 = clk1;
G1_q_b[1]_clock_enable_0 = wren;
G1_q_b[1]_PORT_B_data_out = MEMORY(G1_q_b[1]_PORT_A_data_in_reg, , G1_q_b[1]_PORT_A_address_reg, G1_q_b[1]_PORT_B_address_reg, G1_q_b[1]_PORT_A_write_enable_reg, G1_q_b[1]_PORT_B_read_enable_reg, , , G1_q_b[1]_clock_0, G1_q_b[1]_clock_1, G1_q_b[1]_clock_enable_0, , , );
G1_q_b[1] = G1_q_b[1]_PORT_B_data_out[0];


--G1_q_b[0] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[0]_PORT_A_data_in = E1_result[0];
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = clk1;
G1_q_b[0]_clock_1 = clk1;
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[0] = G1_q_b[0]_PORT_B_data_out[0];


--E1_result[0] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[0]
--DSP Block Operation Mode: Simple Multiplier (9-bit)
E1_result[0] = E1_mac_mult2;

--E1_result[1] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[1]
E1_result[1] = E1L2Q;

--E1_result[2] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[2]
E1_result[2] = E1L3Q;

--E1_result[3] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[3]
E1_result[3] = E1L4Q;

--E1_result[4] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[4]
E1_result[4] = E1L5Q;

--E1_result[5] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[5]
E1_result[5] = E1L6Q;

--E1_result[6] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[6]
E1_result[6] = E1L7Q;

--E1_result[7] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[7]
E1_result[7] = E1L8Q;

--E1_result[8] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[8]
E1_result[8] = E1L9Q;

--E1_result[9] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[9]
E1_result[9] = E1L01Q;

--E1_result[10] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[10]
E1_result[10] = E1L11Q;

--E1_result[11] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[11]
E1_result[11] = E1L21Q;

--E1_result[12] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[12]
E1_result[12] = E1L31Q;

--E1_result[13] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[13]
E1_result[13] = E1L41Q;

--E1_result[14] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[14]
E1_result[14] = E1L51Q;

--E1_result[15] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[15]
E1_result[15] = E1L61Q;


--C1L1Q is ram:inst1|ram_block~0
C1L1Q = DFFEAS(rdaddress[0], clk1,  ,  ,  ,  ,  ,  ,  );


--C1L2Q is ram:inst1|ram_block~1
C1L2Q = DFFEAS(rdaddress[1], clk1,  ,  ,  ,  ,  ,  ,  );


--C1L3Q is ram:inst1|ram_block~2
C1L3Q = DFFEAS(rdaddress[2], clk1,  ,  ,  ,  ,  ,  ,  );


--C1L4Q is ram:inst1|ram_block~3
C1L4Q = DFFEAS(rdaddress[3], clk1,  ,  ,  ,  ,  ,  ,  );


--C1L5Q is ram:inst1|ram_block~4
C1L5Q = DFFEAS(rdaddress[4], clk1,  ,  ,  ,  ,  ,  ,  );


--E1_mac_mult2 is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2
--DSP Block Multiplier Base Width: 9-bits
E1_mac_mult2_a_data = DATA(dataa[7], dataa[6], dataa[5], dataa[4], dataa[3], dataa[2], dataa[1], dataa[0]);
E1_mac_mult2_a_reg = DFFE(E1_mac_mult2_a_data, clk1, , , );
E1_mac_mult2_a_rep = UNSIGNED(E1_mac_mult2_a_reg);
E1_mac_mult2_b_data = DATA(datab[7], datab[6], datab[5], datab[4], datab[3], datab[2], datab[1], datab[0]);
E1_mac_mult2_b_reg = DFFE(E1_mac_mult2_b_data, clk1, , , );
E1_mac_mult2_b_rep = UNSIGNED(E1_mac_mult2_b_reg);
E1_mac_mult2_result = E1_mac_mult2_a_rep * E1_mac_mult2_b_rep;
E1_mac_mult2_round = E1_mac_mult2_result;
E1_mac_mult2_saturate = E1_mac_mult2_round;
E1_mac_mult2_result_reg = DFFE(E1_mac_mult2_saturate, clk1, , , );
E1_mac_mult2 = E1_mac_mult2_result_reg[0];

--E1L2Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT1
E1L2Q = E1_mac_mult2_result_reg[1];

--E1L3Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2
E1L3Q = E1_mac_mult2_result_reg[2];

--E1L4Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT3
E1L4Q = E1_mac_mult2_result_reg[3];

--E1L5Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT4
E1L5Q = E1_mac_mult2_result_reg[4];

--E1L6Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT5
E1L6Q = E1_mac_mult2_result_reg[5];

--E1L7Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT6
E1L7Q = E1_mac_mult2_result_reg[6];

--E1L8Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT7
E1L8Q = E1_mac_mult2_result_reg[7];

--E1L9Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT8
E1L9Q = E1_mac_mult2_result_reg[8];

--E1L01Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT9
E1L01Q = E1_mac_mult2_result_reg[9];

--E1L11Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT10
E1L11Q = E1_mac_mult2_result_reg[10];

--E1L21Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT11
E1L21Q = E1_mac_mult2_result_reg[11];

--E1L31Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT12
E1L31Q = E1_mac_mult2_result_reg[12];

--E1L41Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT13
E1L41Q = E1_mac_mult2_result_reg[13];

--E1L51Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT14
E1L51Q = E1_mac_mult2_result_reg[14];

--E1L61Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT15
E1L61Q = E1_mac_mult2_result_reg[15];


--clk1 is clk1
--operation mode is input

clk1 = INPUT();


--wren is wren
--operation mode is input

wren = INPUT();


--wraddress[0] is wraddress[0]