_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity empty_flag_reg_v2 is
    generic(
        addr_width      : integer := 6;
        c_enable_rlocs  : integer := 0
    );
    port(
        rst             : in     vl_logic;
        flag_clk        : in     vl_logic;
        flag_ce1        : in     vl_logic;
        flag_ce2        : in     vl_logic;
        reg_clk         : in     vl_logic;
        reg_ce          : in     vl_logic;
        a_in            : in     vl_logic_vector;
        b_in            : in     vl_logic_vector;
        dlyd_out        : out    vl_logic_vector;
        flag_out        : out    vl_logic;
        to_almost_logic : out    vl_logic
    );
end empty_flag_reg_v2;