_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_hand_shaking_v2_0 is
    generic(
        memory_architecture: integer := 1;
        init_value      : string  := "000000"
    );
    port(
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        reset           : in     vl_logic;
        start           : in     vl_logic;
        result_avail    : in     vl_logic;
        eio_pulse_out   : in     vl_logic;
        busy            : out    vl_logic;
        done            : out    vl_logic;
        edone           : out    vl_logic
    );
end vfft32_hand_shaking_v2_0;