_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity cmpsvht is
    generic(
        create_rpm      : integer := 0;
        port_width      : integer := 8;
        twos_complement : integer := 1
    );
    port(
        a               : in     vl_logic_vector;
        inv             : in     vl_logic;
        c               : in     vl_logic;
        ce              : in     vl_logic;
        q               : out    vl_logic_vector
    );
end cmpsvht;