_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 33 行

library verilog;
use verilog.vl_types.all;
entity rs_encoder_v2_0 is
    generic(
        c_gen_start     : integer := 0;
        c_h             : integer := 1;
        c_k             : integer := 188;
        c_memstyle      : integer := 2;
        c_n             : integer := 204;
        c_optimization  : integer := 1;
        c_polynomial    : integer := 0;
        c_spec          : integer := 0;
        c_symbol_width  : integer := 8;
        c_userpm        : integer := 1;
        output_delay    : integer := 1;
        ioi1l1i1ollloo1i1l011l0i1l: integer := 1;
        ioo0loill1lo0i1010l0loi00o: integer := 0;
        iil10ooiliil1loiolollooill: integer := 0;
        ii0o1l1loll01lo1o0li1olloi: integer := 1;
        iiii0ll1l1oi010l1lllll1l0l: integer := 12
    );
    port(
        bypass          : in     vl_logic;
        clk             : in     vl_logic;
        data_in         : in     vl_logic_vector;
        data_out        : out    vl_logic_vector;
        enable          : in     vl_logic;
        info            : out    vl_logic;
        reset           : in     vl_logic;
        start           : in     vl_logic
    );
end rs_encoder_v2_0;