_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_bfly_buffer_v2_0 is
    generic(
        bfly_width      : integer := 12;
        memory_configuration: integer := 3;
        one_string      : string  := "01";
        ainit_val       : string  := "00";
        sinit_val       : string  := "00";
        ascii_zero      : integer := 48
    );
    port(
        by0             : in     vl_logic_vector;
        by1             : in     vl_logic_vector;
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        start           : in     vl_logic;
        e_start         : in     vl_logic;
        fft4y0          : out    vl_logic_vector;
        fft4y1          : out    vl_logic_vector;
        fft4y2          : out    vl_logic_vector;
        fft4y3          : out    vl_logic_vector
    );
end vfft32_bfly_buffer_v2_0;