_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity c_mux_slice_bufe_v5_0 is
    generic(
        c_width         : integer := 16
    );
    port(
        i               : in     vl_logic_vector;
        oe              : in     vl_logic;
        o               : out    vl_logic_vector
    );
end c_mux_slice_bufe_v5_0;