_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_mem_wkg_r_i_v2_0 is
    generic(
        b               : integer := 12;
        points_power    : integer := 5;
        default_data    : integer := 48
    );
    port(
        addra           : in     vl_logic_vector;
        wea             : in     vl_logic;
        ena             : in     vl_logic;
        dia_r           : in     vl_logic_vector;
        dia_i           : in     vl_logic_vector;
        reset           : in     vl_logic;
        clk             : in     vl_logic;
        addrb           : in     vl_logic_vector;
        web             : in     vl_logic;
        enb             : in     vl_logic;
        dib_r           : in     vl_logic_vector;
        dib_i           : in     vl_logic_vector;
        dob_r           : out    vl_logic_vector;
        dob_i           : out    vl_logic_vector
    );
end vfft32_mem_wkg_r_i_v2_0;