_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity iobufndn_24 is
    port(
        o               : out    vl_logic;
        io              : inout  vl_logic;
        i               : in     vl_logic
    );
end iobufndn_24;