_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity osc4 is
    generic(
        cds_action      : string  := "ignore";
        period          : integer := 100
    );
    port(
        f8m             : out    vl_logic;
        f500k           : out    vl_logic;
        f16k            : out    vl_logic;
        f490            : out    vl_logic;
        f15             : out    vl_logic
    );
end osc4;