_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity icap_virtex2 is
    generic(
        cds_action      : string  := "ignore"
    );
    port(
        busy            : out    vl_logic;
        o               : out    vl_logic_vector(7 downto 0);
        ce              : in     vl_logic;
        clk             : in     vl_logic;
        i               : in     vl_logic_vector(7 downto 0);
        write           : in     vl_logic
    );
end icap_virtex2;