_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity fpga_startup is
    port(
        bus_reset       : out    vl_logic;
        ghigh_b         : out    vl_logic;
        gsr             : out    vl_logic;
        done            : out    vl_logic;
        gwe             : out    vl_logic;
        gts_b           : out    vl_logic;
        shutdown        : in     vl_logic;
        cclk            : in     vl_logic;
        por             : in     vl_logic
    );
end fpga_startup;