📄 cnt99.rpt
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Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------- LC25 coutp
| +--------------------- LC27 enable
| | +------------------- LC29 |LPM_ADD_SUB:196|addcore:adder|addcore:adder0|result_node2
| | | +----------------- LC26 ss
| | | | +--------------- LC24 y00
| | | | | +------------- LC22 y01
| | | | | | +----------- LC21 y02
| | | | | | | +--------- LC19 y03
| | | | | | | | +------- LC17 y10
| | | | | | | | | +----- LC23 y11
| | | | | | | | | | +--- LC18 y12
| | | | | | | | | | | +- LC20 y13
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC29 -> - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:196|addcore:adder|addcore:adder0|result_node2
LC24 -> * * * * * * * * * * * * | - * | <-- y00
LC22 -> * * * * * * * * * * * * | - * | <-- y01
LC21 -> * * * * * - * * * * * * | - * | <-- y02
LC19 -> * * - * * * * * * * * * | - * | <-- y03
LC17 -> - * - * - - - - * * * * | - * | <-- y10
LC23 -> - * - * - - - - * * * * | - * | <-- y11
LC18 -> - * - * - - - - * - * * | - * | <-- y12
LC20 -> - * - * - - - - * * * * | - * | <-- y13
Pin
43 -> - - - - - - - - - - - - | - - | <-- clk2
11 -> - - - - * - - - - - - - | - * | <-- d0
9 -> - - - - - * - - - - - - | - * | <-- d1
8 -> - - - - - - * - - - - - | - * | <-- d2
7 -> - - - - - - - * - - - - | - * | <-- d3
5 -> - - - - * * * * - - - - | - * | <-- load2
4 -> - - - - * * * * * * * * | - * | <-- reset2
6 -> - - - - * * * * * * * * | - * | <-- updownp
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\741\2502144\02502144\cnt99.rpt
cnt99
** EQUATIONS **
clk2 : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
load2 : INPUT;
reset2 : INPUT;
updownp : INPUT;
-- Node name is 'coutp'
-- Equation name is 'coutp', location is LC025, type is output.
coutp = LCELL( _EQ001 $ GND);
_EQ001 = y00 & !y01 & !y02 & y03;
-- Node name is 'enable'
-- Equation name is 'enable', location is LC027, type is output.
enable = LCELL( _EQ002 $ VCC);
_EQ002 = !y01 & !y02 & !y03 & !y10 & !y11 & !y12 & !y13
# !y00 & !y02 & !y03 & !y10 & !y11 & !y12 & !y13;
-- Node name is 'ss'
-- Equation name is 'ss', location is LC026, type is output.
ss = LCELL( _EQ003 $ GND);
_EQ003 = y00 & !y01 & !y02 & y03 & y10 & !y11 & !y12 & y13;
-- Node name is 'y00' = 'bb0'
-- Equation name is 'y00', location is LC024, type is output.
y00 = DFFE( _EQ004 $ GND, GLOBAL( clk2), !_EQ005, !_EQ006, updownp);
_EQ004 = !y00 & !y01 & !y02 & y03
# !y00 & !y03;
_EQ005 = _X001 & _X002;
_X001 = EXP( d0 & !reset2);
_X002 = EXP(!load2 & !reset2);
_EQ006 = d0 & load2;
-- Node name is 'y01' = 'bb1'
-- Equation name is 'y01', location is LC022, type is output.
y01 = DFFE( _EQ007 $ GND, GLOBAL( clk2), !_EQ008, !_EQ009, updownp);
_EQ007 = !y00 & y01 & !y03
# y00 & !y01 & !y03;
_EQ008 = _X002 & _X003;
_X002 = EXP(!load2 & !reset2);
_X003 = EXP( d1 & !reset2);
_EQ009 = d1 & load2;
-- Node name is 'y02' = 'bb2'
-- Equation name is 'y02', location is LC021, type is output.
y02 = DFFE( _EQ010 $ GND, GLOBAL( clk2), !_EQ011, !_EQ012, updownp);
_EQ010 = _LC029 & !y00 & !y01 & !y02 & y03
# _LC029 & !y03;
_EQ011 = _X002 & _X004;
_X002 = EXP(!load2 & !reset2);
_X004 = EXP( d2 & !reset2);
_EQ012 = d2 & load2;
-- Node name is 'y03' = 'bb3'
-- Equation name is 'y03', location is LC019, type is output.
y03 = DFFE( _EQ013 $ GND, GLOBAL( clk2), !_EQ014, !_EQ015, updownp);
_EQ013 = _X005 & !y00 & !y01 & !y02 & y03
# y00 & y01 & y02 & !y03;
_X005 = EXP( y00 & y01 & y02);
_EQ014 = _X002 & _X006;
_X002 = EXP(!load2 & !reset2);
_X006 = EXP( d3 & !reset2);
_EQ015 = d3 & load2;
-- Node name is 'y10' = 'kk0'
-- Equation name is 'y10', location is LC017, type is output.
y10 = TFFE( _EQ016, GLOBAL( clk2), !reset2, VCC, updownp);
_EQ016 = y00 & !y01 & !y02 & y03 & !y10 & !y11 & !y12 & y13
# y00 & !y01 & !y02 & y03 & !y10 & !y13
# y00 & !y01 & !y02 & y03 & y10;
-- Node name is 'y11' = 'kk1'
-- Equation name is 'y11', location is LC023, type is output.
y11 = TFFE( _EQ017, GLOBAL( clk2), !reset2, VCC, updownp);
_EQ017 = y00 & !y01 & !y02 & y03 & y10 & !y11 & !y13
# y00 & !y01 & !y02 & y03 & y10 & y11
# y00 & !y01 & !y02 & y03 & y11 & y13;
-- Node name is 'y12' = 'kk2'
-- Equation name is 'y12', location is LC018, type is output.
y12 = TFFE( _EQ018, GLOBAL( clk2), !reset2, VCC, updownp);
_EQ018 = y00 & !y01 & !y02 & y03 & y10 & y11 & !y12 & !y13
# y00 & !y01 & !y02 & y03 & y10 & y11 & y12
# y00 & !y01 & !y02 & y03 & y12 & y13;
-- Node name is 'y13' = 'kk3'
-- Equation name is 'y13', location is LC020, type is output.
y13 = TFFE( _EQ019, GLOBAL( clk2), !reset2, VCC, updownp);
_EQ019 = y00 & !y01 & !y02 & y03 & y10 & y11 & y12
# _X007 & y00 & !y01 & !y02 & y03 & y13;
_X007 = EXP(!y10 & !y11 & !y12);
-- Node name is '|LPM_ADD_SUB:196|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( y02 $ _EQ020);
_EQ020 = y00 & y01;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\741\2502144\02502144\cnt99.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,504K
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