cnt10.vhd

来自「在本示例程序中」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
    port(clk0,reset0,updown:in std_logic;
                      cout:out std_logic;
     q:out std_logic_vector(3 downto 0 ));
end;
architecture behav of cnt10 is
signal  cq :std_logic_vector(3 downto 0);
begin
process(clk0,reset0,updown)
begin
if reset0='1' then cq<=(others=>'0');
elsif updown='0' then cq<=cq;
elsif clk0'event and clk0='1' then
if cq<"1001" then cq<=cq+1;
     else cq<=(others=>'0');
end if;
end if;
if cq="1001" then cout<='1';
    else cout<='0';
end if;
q<=cq;
end process;
end behav;