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📄 jifei.rpt

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-- synthesized logic cell 
_LC6_B5  = LCELL( _EQ035);
  _EQ035 =  _LC1_B4 & !_LC5_B13
         #  _LC1_B4 &  _LC4_B5;

-- Node name is '|cnt99:u3|:495' 
-- Equation name is '_LC2_B13', type is buried 
_LC2_B13 = LCELL( _EQ036);
  _EQ036 = !_LC1_B13 &  _LC5_B13 &  _LC6_B5
         # !_LC2_B5 &  _LC5_B13 &  _LC6_B5
         #  _LC1_B13 &  _LC2_B5 & !_LC5_B13 &  _LC6_B5;

-- Node name is '|cnt99:u3|:501' 
-- Equation name is '_LC8_B5', type is buried 
_LC8_B5  = LCELL( _EQ037);
  _EQ037 = !_LC1_B5 &  _LC2_B5 &  _LC6_B5
         #  _LC2_B5 & !_LC3_B5 &  _LC6_B5
         #  _LC1_B5 & !_LC2_B5 &  _LC3_B5 &  _LC6_B5;

-- Node name is '|cnt99:u3|:507' 
-- Equation name is '_LC7_B5', type is buried 
_LC7_B5  = LCELL( _EQ038);
  _EQ038 =  _LC1_B5 & !_LC3_B5 &  _LC6_B5
         # !_LC1_B5 &  _LC3_B5 &  _LC6_B5;

-- Node name is '|cnt99:u5|:27' = '|cnt99:u5|bb0' 
-- Equation name is '_LC3_C23', type is buried 
_LC3_C23 = DFFE( _EQ039,  _LC1_B21, !reset & !(GLOBAL( pg) & !aq0), !(GLOBAL( pg) &  aq0),  up_down);
  _EQ039 = !_LC3_C23 &  _LC4_C23;

-- Node name is '|cnt99:u5|:26' = '|cnt99:u5|bb1' 
-- Equation name is '_LC1_C23', type is buried 
_LC1_C23 = DFFE( _EQ040,  _LC1_B21, !reset & !(GLOBAL( pg) & !aq1), !(GLOBAL( pg) &  aq1),  up_down);
  _EQ040 =  _LC4_C23 &  _LC5_C23;

-- Node name is '|cnt99:u5|:25' = '|cnt99:u5|bb2' 
-- Equation name is '_LC2_C23', type is buried 
_LC2_C23 = DFFE( _EQ041,  _LC1_B21, !reset & !(GLOBAL( pg) & !aq2), !(GLOBAL( pg) &  aq2),  up_down);
  _EQ041 =  _LC4_C23 &  _LC7_C23;

-- Node name is '|cnt99:u5|:24' = '|cnt99:u5|bb3' 
-- Equation name is '_LC6_C23', type is buried 
_LC6_C23 = DFFE( _LC8_C23,  _LC1_B21, !reset & !(GLOBAL( pg) & !aq3), !(GLOBAL( pg) &  aq3),  up_down);

-- Node name is '|cnt99:u5|:23' = '|cnt99:u5|kk0' 
-- Equation name is '_LC1_B10', type is buried 
_LC1_B10 = DFFE( _EQ042,  _LC1_B21, !reset,  VCC,  up_down);
  _EQ042 = !_LC1_B10 &  _LC6_B10
         #  _LC1_B10 & !_LC3_B2;

-- Node name is '|cnt99:u5|:22' = '|cnt99:u5|kk1' 
-- Equation name is '_LC8_B2', type is buried 
_LC8_B2  = DFFE( _EQ043,  _LC1_B21, !reset,  VCC,  up_down);
  _EQ043 =  _LC2_B10
         # !_LC3_B2 &  _LC8_B2;

-- Node name is '|cnt99:u5|:21' = '|cnt99:u5|kk2' 
-- Equation name is '_LC4_B10', type is buried 
_LC4_B10 = DFFE( _EQ044,  _LC1_B21, !reset,  VCC,  up_down);
  _EQ044 =  _LC7_B10
         # !_LC3_B2 &  _LC4_B10;

-- Node name is '|cnt99:u5|:20' = '|cnt99:u5|kk3' 
-- Equation name is '_LC5_B10', type is buried 
_LC5_B10 = DFFE( _EQ045,  _LC1_B21, !reset,  VCC,  up_down);
  _EQ045 =  _LC8_B10
         # !_LC3_B2 &  _LC5_B10;

-- Node name is '|cnt99:u5|LPM_ADD_SUB:196|addcore:adder|:67' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_C23', type is buried 
_LC5_C23 = LCELL( _EQ046);
  _EQ046 =  _LC1_C23 & !_LC3_C23
         # !_LC1_C23 &  _LC3_C23;

-- Node name is '|cnt99:u5|LPM_ADD_SUB:196|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_C23', type is buried 
_LC7_C23 = LCELL( _EQ047);
  _EQ047 = !_LC1_C23 &  _LC2_C23
         #  _LC2_C23 & !_LC3_C23
         #  _LC1_C23 & !_LC2_C23 &  _LC3_C23;

-- Node name is '|cnt99:u5|LPM_ADD_SUB:434|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B12', type is buried 
_LC1_B12 = LCELL( _EQ048);
  _EQ048 =  _LC1_B10 &  _LC8_B2;

-- Node name is '|cnt99:u5|:167' 
-- Equation name is '_LC4_C23', type is buried 
_LC4_C23 = LCELL( _EQ049);
  _EQ049 = !_LC6_C23
         # !_LC1_C23 & !_LC2_C23 & !_LC3_C23;

-- Node name is '|cnt99:u5|:223' 
-- Equation name is '_LC8_C23', type is buried 
_LC8_C23 = LCELL( _EQ050);
  _EQ050 =  _LC1_C23 &  _LC2_C23 &  _LC3_C23 & !_LC6_C23
         # !_LC1_C23 & !_LC2_C23 & !_LC3_C23 &  _LC6_C23;

-- Node name is '|cnt99:u5|:391' 
-- Equation name is '_LC3_B2', type is buried 
!_LC3_B2 = _LC3_B2~NOT;
_LC3_B2~NOT = LCELL( _EQ051);
  _EQ051 = !_LC3_C23
         # !_LC6_C23
         #  _LC2_C23
         #  _LC1_C23;

-- Node name is '|cnt99:u5|:407' 
-- Equation name is '_LC3_B10', type is buried 
!_LC3_B10 = _LC3_B10~NOT;
_LC3_B10~NOT = LCELL( _EQ052);
  _EQ052 =  _LC1_B10
         #  _LC4_B10
         #  _LC8_B2;

-- Node name is '|cnt99:u5|~495~1' 
-- Equation name is '_LC6_B10', type is buried 
-- synthesized logic cell 
_LC6_B10 = LCELL( _EQ053);
  _EQ053 =  _LC3_B2 & !_LC5_B10
         #  _LC3_B2 &  _LC3_B10;

-- Node name is '|cnt99:u5|:495' 
-- Equation name is '_LC8_B10', type is buried 
_LC8_B10 = LCELL( _EQ054);
  _EQ054 = !_LC1_B12 &  _LC5_B10 &  _LC6_B10
         # !_LC4_B10 &  _LC5_B10 &  _LC6_B10
         #  _LC1_B12 &  _LC4_B10 & !_LC5_B10 &  _LC6_B10;

-- Node name is '|cnt99:u5|:501' 
-- Equation name is '_LC7_B10', type is buried 
_LC7_B10 = LCELL( _EQ055);
  _EQ055 =  _LC4_B10 &  _LC6_B10 & !_LC8_B2
         # !_LC1_B10 &  _LC4_B10 &  _LC6_B10
         #  _LC1_B10 & !_LC4_B10 &  _LC6_B10 &  _LC8_B2;

-- Node name is '|cnt99:u5|:507' 
-- Equation name is '_LC2_B10', type is buried 
_LC2_B10 = LCELL( _EQ056);
  _EQ056 = !_LC1_B10 &  _LC6_B10 &  _LC8_B2
         #  _LC1_B10 &  _LC6_B10 & !_LC8_B2;

-- Node name is '|cnt99:u5|~533~1' 
-- Equation name is '_LC2_B2', type is buried 
-- synthesized logic cell 
_LC2_B2  = LCELL( _EQ057);
  _EQ057 =  _LC6_C23
         #  _LC2_C23
         #  _LC5_B10;

-- Node name is '|cnt99:u5|:533' 
-- Equation name is '_LC6_B2', type is buried 
!_LC6_B2 = _LC6_B2~NOT;
_LC6_B2~NOT = LCELL( _EQ058);
  _EQ058 = !_LC3_B10
         #  _LC2_B2
         #  _LC1_C23 &  _LC3_C23;

-- Node name is '|Fenpin16:u1|:8' = '|Fenpin16:u1|tmp0' 
-- Equation name is '_LC1_B8', type is buried 
_LC1_B8  = DFFE(!_LC1_B8, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|Fenpin16:u1|:7' = '|Fenpin16:u1|tmp1' 
-- Equation name is '_LC2_B8', type is buried 
_LC2_B8  = DFFE( _EQ059, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ059 =  _LC1_B8 & !_LC2_B8
         # !_LC1_B8 &  _LC2_B8;

-- Node name is '|Fenpin16:u1|:6' = '|Fenpin16:u1|tmp2' 
-- Equation name is '_LC3_B8', type is buried 
_LC3_B8  = DFFE( _EQ060, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ060 = !_LC1_B8 &  _LC3_B8
         # !_LC2_B8 &  _LC3_B8
         #  _LC1_B8 &  _LC2_B8 & !_LC3_B8;

-- Node name is '|Fenpin16:u1|:5' = '|Fenpin16:u1|tmp3' 
-- Equation name is '_LC4_B8', type is buried 
_LC4_B8  = DFFE( _EQ061, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ061 = !_LC3_B8 &  _LC4_B8
         # !_LC1_B8 &  _LC4_B8
         # !_LC2_B8 &  _LC4_B8
         #  _LC1_B8 &  _LC2_B8 &  _LC3_B8 & !_LC4_B8;

-- Node name is '|Fenpin16:u1|~152~1' 
-- Equation name is '_LC6_B8', type is buried 
-- synthesized logic cell 
_LC6_B8  = LCELL( _EQ062);
  _EQ062 =  ko2 &  _LC1_B8
         # !ko2 &  _LC2_B8;

-- Node name is '|Fenpin16:u1|~152~2' 
-- Equation name is '_LC7_B8', type is buried 
-- synthesized logic cell 
_LC7_B8  = LCELL( _EQ063);
  _EQ063 =  ko2 &  _LC3_B8
         # !ko2 &  _LC4_B8;

-- Node name is '|Fenpin16:u1|:152' 
-- Equation name is '_LC5_B8', type is buried 
_LC5_B8  = LCELL( _EQ064);
  _EQ064 =  ko1 &  _LC6_B8
         # !ko1 &  _LC7_B8;



Project Information                              f:\2502144\02502144\jifei.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,597K

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